JPS643911U - - Google Patents

Info

Publication number
JPS643911U
JPS643911U JP9850087U JP9850087U JPS643911U JP S643911 U JPS643911 U JP S643911U JP 9850087 U JP9850087 U JP 9850087U JP 9850087 U JP9850087 U JP 9850087U JP S643911 U JPS643911 U JP S643911U
Authority
JP
Japan
Prior art keywords
contact switch
input terminal
input
contact
input end
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9850087U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9850087U priority Critical patent/JPS643911U/ja
Publication of JPS643911U publication Critical patent/JPS643911U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例に係る四方向制御装
置の回路構成図、第2図は第1図に示した同上回
路において第1の接点スイツチをオンにした場合
における各部の入出力状態表示記号を付加して示
した回路図、第3図は第1図に示した同上回路に
おいて第2の接点スイツチをオンした場合におけ
る各部の入出力状態表示記号を付加して示した回
路図、第4図は第2図に示した同上回路において
さらに第3のスイツチをオンした場合における各
部の入出力状態表示記号を付加して示した回路図
、第5図は第1図乃至第4図に示した同上装置で
使用可能なスイツチユニツトの一実施例における
スイツチユニツトの正面図、第6図は第5図のA
―A線に沿う同上ユニツトの断面図、第7図は同
上ユニツトにおける絶縁基板単品の平面図、第8
図は同上ユニツトにおける押圧ノブ単品の底面図
である。 1…スイツチユニツト、36…第1の接点スイ
ツチ、37…第2の接点スイツチ、38…第3の
接点スイツチ、39…第4の接点スイツチ、41
…第1のモータ(被制御手段)、42…第2のモ
ータ(被制御手段)、50…第1のAND回路、
51…第2のAND回路、52…第3のAND回
路、53…第4のAND回路。
Figure 1 is a circuit configuration diagram of a four-way control device according to an embodiment of the present invention, and Figure 2 is the input/output state of each part in the same circuit shown in Figure 1 when the first contact switch is turned on. FIG. 3 is a circuit diagram with display symbols added, and FIG. 3 is a circuit diagram with input/output status display symbols of each part when the second contact switch is turned on in the same circuit shown in FIG. Figure 4 is a circuit diagram of the same circuit shown in Figure 2 with input/output status display symbols for each part added when the third switch is turned on, and Figure 5 is a circuit diagram of the circuit shown in Figures 1 to 4. FIG. 6 is a front view of a switch unit in an embodiment of the switch unit that can be used in the above device shown in FIG.
- A cross-sectional view of the above unit along line A, Figure 7 is a plan view of a single insulating substrate in the same unit, and Figure 8 is a cross-sectional view of the above unit.
The figure is a bottom view of a single press knob in the same unit. DESCRIPTION OF SYMBOLS 1... Switch unit, 36... First contact switch, 37... Second contact switch, 38... Third contact switch, 39... Fourth contact switch, 41
...first motor (controlled means), 42...second motor (controlled means), 50...first AND circuit,
51...Second AND circuit, 52...Third AND circuit, 53...Fourth AND circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 異なる第1、第2、第3、第4の4つの接点ス
イツチで被制御手段を四方向へ切り換え制御する
四方向制御装置であつて、各々第1、第2、第3
、第4の4入力端を有する第1、第2、第3、第
4のAND回路を備えて前記各AND回路の出力
で前記被制御手段を異なる方向へ制御する論理回
路を構成し、前記第1のAND回路が前記第1の
接点スイツチに前記第1の入力端を、前記第4の
接点スイツチに前記第2の入力端を、前記第2の
接点スイツチに前記第3の入力端を、前記第3の
接点スイツチに前記第4の入力端をそれぞれ接続
し、前記第2のAND回路が前記第3の接点スイ
ツチに前記第1の入力端を、前記第2の接点スイ
ツチに前記第2の入力端を、前記第4の接点スイ
ツチに前記第3の入力端を、前記第1の接点スイ
ツチに前記第4の入力端をそれぞれ接続し、前記
第3のAND回路が前記第2の接点スイツチに前
記第1の入力端を、前記第3の接点スイツチに前
記第2の入力端を、前記第4の接点スイツチに前
記第3の入力端を、前記第1の接点スイツチに前
記第4の入力端をそれぞれ接続し、前記第4のA
ND回路が前記第4の接点スイツチに前記第1の
入力端を、前記第3の接点スイツチに前記第2の
入力端を、前記第2の接点スイツチに前記第3の
入力端を、前記第1の接点スイツチに前記第4の
入力端をそれぞれ接続してなり、かつ前記各AN
D回路の前記第1の入力端を他の前記第2、第3
、第4の入力端に対して逆特性で形成し前記各入
力端に入力する信号を各々反転入力処理するとと
もに、前記各接点スイツチが並行操作された場合
に前記被制御手段の操作を停止することを特徴と
する四方向制御装置。
A four-way control device that switches and controls a controlled means in four directions using four different first, second, third, and fourth contact switches, each of which has a first, second, third, and fourth contact switch.
, a logic circuit comprising first, second, third, and fourth AND circuits each having four input terminals and controlling the controlled means in different directions with the output of each of the AND circuits; A first AND circuit connects the first input end to the first contact switch, the second input end to the fourth contact switch, and the third input end to the second contact switch. , the fourth input terminal is connected to the third contact switch, and the second AND circuit connects the first input terminal to the third contact switch and the fourth input terminal to the second contact switch. The second input terminal is connected to the second contact switch, the third input terminal is connected to the fourth contact switch, and the fourth input terminal is connected to the first contact switch, and the third AND circuit connects the second input terminal to the fourth contact switch. The first input end is connected to the contact switch, the second input end is connected to the third contact switch, the third input end is connected to the fourth contact switch, and the third input end is connected to the first contact switch. 4 input terminals are connected respectively, and the fourth A
An ND circuit connects the first input terminal to the fourth contact switch, the second input terminal to the third contact switch, the third input terminal to the second contact switch, and the third input terminal to the third contact switch. the fourth input terminal is connected to one contact switch, and each of the AN
The first input terminal of the D circuit is connected to the other second and third input terminals.
, which is formed with an inverse characteristic to the fourth input terminal and performs inverted input processing on the signals inputted to each input terminal, and stops the operation of the controlled means when each of the contact switches is operated in parallel. A four-way control device characterized by:
JP9850087U 1987-06-29 1987-06-29 Pending JPS643911U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9850087U JPS643911U (en) 1987-06-29 1987-06-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9850087U JPS643911U (en) 1987-06-29 1987-06-29

Publications (1)

Publication Number Publication Date
JPS643911U true JPS643911U (en) 1989-01-11

Family

ID=31324826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9850087U Pending JPS643911U (en) 1987-06-29 1987-06-29

Country Status (1)

Country Link
JP (1) JPS643911U (en)

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