JPS647313U - - Google Patents

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Publication number
JPS647313U
JPS647313U JP9942887U JP9942887U JPS647313U JP S647313 U JPS647313 U JP S647313U JP 9942887 U JP9942887 U JP 9942887U JP 9942887 U JP9942887 U JP 9942887U JP S647313 U JPS647313 U JP S647313U
Authority
JP
Japan
Prior art keywords
circuit
input terminal
contact switch
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9942887U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9942887U priority Critical patent/JPS647313U/ja
Publication of JPS647313U publication Critical patent/JPS647313U/ja
Pending legal-status Critical Current

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  • Control Of Position Or Direction (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例に係る四方向制御装
置の回路構成図、第2図は第1図に示した同上回
路において第1と第2の接点スイツチをオンした
場合における各部の入出力状態表示記号を付加し
て示した回路図、第3図は第1図に示した同上回
路において第1と第3の接点スイツチをオンした
場合における各部の入出力状態表示記号を付加し
て示した回路図、第4図は第2図に示した同上回
路においてさらに第3と第4のスイツチをオンし
た場合における各部の入出力状態表示記号を付加
して示した回路図、第5図は第1図乃至第4図に
示した同上装置で使用可能なスイツチユニツトの
一実施例におけるスイツチユニツトの正面図、第
6図は第5図のA―A線に沿う同上ユニツトの断
面図、第7図は同上ユニツトにおける絶縁基板単
品の平面図、第8図は同上ユニツトにおける押圧
ノブ単品の底面図である。 1……スイツチユニツト、36……第1の接点
スイツチ、37……第2の接点スイツチ、38…
…第3の接点スイツチ、39……第4の接点スイ
ツチ、41……第1のモータ(被制御手段)、4
2……第2のモータ(被制御手段)、50……第
1のAND回路、51……第2のAND回路、5
2……第3のAND回路、53……第4のAND
回路。
Fig. 1 is a circuit diagram of a four-way control device according to an embodiment of the present invention, and Fig. 2 shows the input of each part in the same circuit shown in Fig. 1 when the first and second contact switches are turned on. Figure 3 is a circuit diagram with output status display symbols added, and Figure 3 is a circuit diagram with input/output status display symbols added for each part when the first and third contact switches are turned on in the same circuit shown in Figure 1. The circuit diagram shown in Fig. 4 is a circuit diagram of the same circuit shown in Fig. 2 with input/output status display symbols for each part added when the third and fourth switches are turned on. Fig. 5 is a front view of an embodiment of the switch unit that can be used in the above device shown in FIGS. 1 to 4; FIG. 6 is a sectional view of the same unit taken along line AA in FIG. 5; FIG. 7 is a plan view of a single insulating substrate in the above unit, and FIG. 8 is a bottom view of a single press knob in the same unit. 1... Switch unit, 36... First contact switch, 37... Second contact switch, 38...
...Third contact switch, 39... Fourth contact switch, 41... First motor (controlled means), 4
2... Second motor (controlled means), 50... First AND circuit, 51... Second AND circuit, 5
2...Third AND circuit, 53...Fourth AND
circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 異なる第1、第2、第3、第4の4つの接点ス
イツチで被制御手段を四方向へ切り換え制御する
四方向制御装置であつて、各々第1、第2、第3
、第4の4入力端を有する第1、第2、第3、第
4のAND回路を備え前記各AND回路の出力で
前記被制御手段を異なる方向へ制御する論理回路
を構成し、前記第1のAND回路が前記第1の入
力端を前記第2の接点スイツチに、前記第2の入
力端を前記第1の接点スイツチにそれぞれ接続し
ているとともに出力端を前記第2のAND回路の
前記第3の入力端と前記第4のAND回路の前記
第3の入力端に接続し、前記第2のAND回路が
前記第1の入力端を前記第4の接点スイツチに、
前記第2の入力端を前記第3の接点スイツチにそ
れぞれ接続しているとともに出力端を前記第1の
AND回路の前記第3の入力端と前記第3のAN
D回路の前記第3の入力端に接続し、前記第3の
AND回路が前記第1の入力端を前記第3の接点
スイツチに、前記第2の入力端を前記第1の接点
スイツチにそれぞれ接続しているとともに出力端
を前記第2のAND回路の前記第4の入力端と前
記第4のAND回路の前記第4の入力端に接続し
、前記第4のAND回路が前記第1の入力端を前
記第4の接点スイツチに、前記第2の入力端を前
記第2の接点スイツチにそれぞれ接続していると
ともに出力端を前記第3のAND回路の前記第4
の入力端と前記第1のAND回路の前記第4の入
力端に接続してなり、かつ前記各AND回路の出
力が前記被制御手段の各制御に干渉し合わないと
き同時出力を行なわせ、干渉するとき後から入力
した前記接点スイツチの入力信号を無効にするこ
とを特徴とする四方向制御装置。
A four-way control device that switches and controls a controlled means in four directions using four different first, second, third, and fourth contact switches, each of which has a first, second, third, and fourth contact switch.
, a logic circuit comprising first, second, third, and fourth AND circuits each having four input terminals, the output of each of the AND circuits controlling the controlled means in different directions; 1 AND circuit connects the first input terminal to the second contact switch, the second input terminal to the first contact switch, and connects the output terminal to the second AND circuit. the third input terminal is connected to the third input terminal of the fourth AND circuit, and the second AND circuit connects the first input terminal to the fourth contact switch;
The second input terminals are connected to the third contact switch, and the output terminals are connected to the third input terminal of the first AND circuit and the third AN.
The third AND circuit is connected to the third input terminal of the D circuit, and the third AND circuit connects the first input terminal to the third contact switch and the second input terminal to the first contact switch. and an output terminal is connected to the fourth input terminal of the second AND circuit and the fourth input terminal of the fourth AND circuit, and the fourth AND circuit is connected to the fourth input terminal of the fourth AND circuit. The input end is connected to the fourth contact switch, the second input end is connected to the second contact switch, and the output end is connected to the fourth contact switch of the third AND circuit.
and the fourth input terminal of the first AND circuit, and perform simultaneous output when the outputs of the respective AND circuits do not interfere with each control of the controlled means, A four-way control device characterized in that when interference occurs, an input signal input later to the contact switch is invalidated.
JP9942887U 1987-06-30 1987-06-30 Pending JPS647313U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9942887U JPS647313U (en) 1987-06-30 1987-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9942887U JPS647313U (en) 1987-06-30 1987-06-30

Publications (1)

Publication Number Publication Date
JPS647313U true JPS647313U (en) 1989-01-17

Family

ID=31326578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9942887U Pending JPS647313U (en) 1987-06-30 1987-06-30

Country Status (1)

Country Link
JP (1) JPS647313U (en)

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