JPS6438877U - - Google Patents
Info
- Publication number
- JPS6438877U JPS6438877U JP13397687U JP13397687U JPS6438877U JP S6438877 U JPS6438877 U JP S6438877U JP 13397687 U JP13397687 U JP 13397687U JP 13397687 U JP13397687 U JP 13397687U JP S6438877 U JPS6438877 U JP S6438877U
- Authority
- JP
- Japan
- Prior art keywords
- horizontal
- circuit
- capacitor
- supplies
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 13
- 238000001514 detection method Methods 0.000 claims description 3
- 230000000737 periodic effect Effects 0.000 claims 2
- 238000004804 winding Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
- 241000226585 Antennaria plantaginifolia Species 0.000 description 1
Landscapes
- Details Of Television Scanning (AREA)
Description
第1図は本考案の水平偏向回路の一実施例を示
す回路図、第2図は本考案の他の実施例を示す回
路図、第3図は従来の水平偏向回路を示す回路図
、第4図は第3図の動作を説明する波形図、第5
図は左右糸巻歪の説明図である。
1……PWM信号入力端子、2……積分用抵抗
、3……積分用コンデンサ、11……可飽和リア
クタ、12……共振コンデンサ、13……ダンパ
ーダイオード、14……水平出力トランジスタ、
15……水平偏向コイル、16……S字補正コン
デンサ、17……フライバツクトランス、18…
…CRT、22,23……高圧検出用抵抗、24
……クランプ用トランジスタ。
FIG. 1 is a circuit diagram showing one embodiment of the horizontal deflection circuit of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the present invention, FIG. 3 is a circuit diagram showing a conventional horizontal deflection circuit, and FIG. Figure 4 is a waveform diagram explaining the operation of Figure 3, and Figure 5 is a waveform diagram explaining the operation of Figure 3.
The figure is an explanatory diagram of left-right pincushion distortion. 1... PWM signal input terminal, 2... Integrating resistor, 3... Integrating capacitor, 11... Saturable reactor, 12... Resonant capacitor, 13... Damper diode, 14... Horizontal output transistor,
15... Horizontal deflection coil, 16... S-shaped correction capacitor, 17... Flyback transformer, 18...
...CRT, 22, 23...High voltage detection resistor, 24
...Clamp transistor.
Claims (1)
パラボラ波作成用のパルス幅変調信号を出力する
デイジタル回路と、 抵抗とコンデンサで構成され、前記デイジタル
回路から出力されるパルス幅変調信号を積分して
垂直周期のパラボラ波信号を作成する積分回路と
、 水平周期でスイツチング動作を行なう水平出力
トランジスタと、ダンパーダイオードと、共振コ
ンデンサとを用いて水平偏向コイルに偏向電力を
供給すると共に、フライバツクトランスを通して
整流した高圧を受像管に供給する水平出力回路と
、 この水平出力回路の前記水平偏向コイルに流れ
る偏向電流の包絡線を、前記積分回路からのパラ
ボラ波信号に基づいて垂直周期でパラボラ状に振
幅変調する補正手段と、 前記受像管に供給される高圧の変動を検出する
検出手段と、 この検出手段からの検出出力に基づいて前記デ
イジタル回路から出力される前記パルス幅変調信
号の波高値を高圧変動に対応したレベルにクラン
プするクランプ回路とを具備したことを特徴とす
る水平振幅補正回路。 (2) 前記水平出力回路は、水平出力トランジス
タのベースに水平周期のドライブパルスを供給し
、そのコレクタ・エミツタ間に対し並列にダンパ
ーダイオード、共振コンデンサが接続し、更に並
列に水平偏向コイルとS字補正コンデンサと水平
振幅補正用トランスを直列にした回路が接続し、
コレクタがフライバツクトランスの1次巻線を通
して直流電源に接続して構成されることを特徴と
する実用新案登録請求の範囲第1項記載の水平振
幅補正回路。 (3) 前記水平出力回路は、水平出力トランジス
タのベースに水平周期のドライブパルスを供給し
、そのコレクタ・エミツタ間に対し並列に第1、
第2の共振コンデンサの直列回路を接続し、第1
、第2の共振コンデンサのそれぞれに並列に第1
、第2のダンパーダイオードを接続し、更に第1
のダンパーダイオードに対して並列に水平偏向コ
イルとS字補正コンデンサの第1の直列回路を接
続し、第2のダンパーダイオードに対して並列に
コイルとコンデンサの第2の直列回路を接続し、
この第2の直列回路のコンデンサの両端電圧を前
記積分回路からのパラボラ波信号に基づいて振幅
変調するように構成したことを特徴とする実用新
案登録請求の範囲第1項記載の水平振幅補正回路
。[Claims for Utility Model Registration] (1) Pulse width modulation of a constant frequency pulse,
a digital circuit that outputs a pulse width modulation signal for creating a parabolic wave; and an integrating circuit that is composed of a resistor and a capacitor and that integrates the pulse width modulation signal output from the digital circuit to create a vertically periodic parabolic wave signal. , a horizontal output circuit that supplies deflection power to the horizontal deflection coil using a horizontal output transistor that performs a switching operation in horizontal cycles, a damper diode, and a resonant capacitor, and also supplies rectified high voltage to the picture tube through a flyback transformer. and a correction means for amplitude modulating the envelope of the deflection current flowing through the horizontal deflection coil of the horizontal output circuit in a parabolic manner with a vertical period based on the parabolic wave signal from the integrating circuit; and a clamp circuit that clamps the peak value of the pulse width modulation signal output from the digital circuit to a level corresponding to the high voltage fluctuation based on the detection output from the detection means. A horizontal amplitude correction circuit characterized by comprising: (2) The horizontal output circuit supplies a drive pulse with a horizontal period to the base of the horizontal output transistor, and a damper diode and a resonant capacitor are connected in parallel between the collector and emitter, and a horizontal deflection coil and an S A circuit in which a horizontal amplitude correction capacitor and a horizontal amplitude correction transformer are connected in series is connected.
2. The horizontal amplitude correction circuit according to claim 1, wherein the collector is connected to a DC power source through a primary winding of a flyback transformer. (3) The horizontal output circuit supplies a horizontally periodic drive pulse to the base of the horizontal output transistor, and supplies a first,
Connect the series circuit of the second resonant capacitor, and
, the first resonant capacitor in parallel with each of the second resonant capacitors.
, the second damper diode is connected, and the first
A first series circuit of a horizontal deflection coil and an S-shaped correction capacitor is connected in parallel to a damper diode, and a second series circuit of a coil and a capacitor is connected in parallel to a second damper diode.
The horizontal amplitude correction circuit according to claim 1, wherein the horizontal amplitude correction circuit is configured to amplitude-modulate the voltage across the capacitor of the second series circuit based on the parabolic wave signal from the integrating circuit. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13397687U JPS6438877U (en) | 1987-09-03 | 1987-09-03 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13397687U JPS6438877U (en) | 1987-09-03 | 1987-09-03 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6438877U true JPS6438877U (en) | 1989-03-08 |
Family
ID=31392334
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13397687U Pending JPS6438877U (en) | 1987-09-03 | 1987-09-03 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6438877U (en) |
-
1987
- 1987-09-03 JP JP13397687U patent/JPS6438877U/ja active Pending
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