JPS6438829U - - Google Patents
Info
- Publication number
- JPS6438829U JPS6438829U JP13325687U JP13325687U JPS6438829U JP S6438829 U JPS6438829 U JP S6438829U JP 13325687 U JP13325687 U JP 13325687U JP 13325687 U JP13325687 U JP 13325687U JP S6438829 U JPS6438829 U JP S6438829U
- Authority
- JP
- Japan
- Prior art keywords
- inverting
- amplifier
- output
- inverting amplifier
- balanced
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Networks Using Active Elements (AREA)
Description
第１図は本考案の一実施例の回路ブロツク図、
第２図は従来例の回路ブロツク図である。
１０……不平衡入力信号、１１……初段増幅器
、１２……非反転増幅器、１３……反転増幅器、
１４，１５……抵抗、１６，１７……平衡出力端
子、１８，１９……低域通過フイルタ、２０，２
１……差動増幅器。
FIG. 1 is a circuit block diagram of an embodiment of the present invention.
FIG. 2 is a circuit block diagram of a conventional example. 10... Unbalanced input signal, 11... First stage amplifier, 12... Non-inverting amplifier, 13... Inverting amplifier,
14,15...Resistor, 16,17...Balanced output terminal, 18,19...Low pass filter, 20,2
1...Differential amplifier.
Claims (1)
力を並列の非反転増幅器と反転増幅器とに入力し
、両増幅器の出力端子間に平衡信号を出力する平
衡出力回路において、 前記非反転および反転増幅器のそれぞれの出力
信号から直流電圧を抽出し、その差電圧を求め、
前記非反転もしくは反転増幅器のいずれかの入力
端子に負帰還させる手段と、前記抽出された直流
電圧のいずれかの電圧を前記初段増幅器の入力端
子に負帰還させる手段と を設けたことを特徴とする平衡出力回路。[Claims for Utility Model Registration] A balanced output circuit that inputs an unbalanced input signal to a first-stage amplifier, inputs its output to a parallel non-inverting amplifier and an inverting amplifier, and outputs a balanced signal between the output terminals of both amplifiers. In, extracting DC voltage from each output signal of the non-inverting and inverting amplifier and finding the difference voltage,
The invention is characterized by comprising means for negatively feeding back any one of the input terminals of the non-inverting or inverting amplifier, and means for negatively feeding any one of the extracted DC voltages to the input terminal of the first stage amplifier. Balanced output circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13325687U JPS6438829U (en) | 1987-09-02 | 1987-09-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13325687U JPS6438829U (en) | 1987-09-02 | 1987-09-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6438829U true JPS6438829U (en) | 1989-03-08 |
Family
ID=31390949
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13325687U Pending JPS6438829U (en) | 1987-09-02 | 1987-09-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6438829U (en) |
-
1987
- 1987-09-02 JP JP13325687U patent/JPS6438829U/ja active Pending
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