JPS643570A - Crest value detector - Google Patents

Crest value detector

Info

Publication number
JPS643570A
JPS643570A JP15835587A JP15835587A JPS643570A JP S643570 A JPS643570 A JP S643570A JP 15835587 A JP15835587 A JP 15835587A JP 15835587 A JP15835587 A JP 15835587A JP S643570 A JPS643570 A JP S643570A
Authority
JP
Japan
Prior art keywords
stage
comparator
flop
bit
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15835587A
Other languages
Japanese (ja)
Inventor
Shigeo Uehara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shibasoku Co Ltd
Original Assignee
Shibasoku Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shibasoku Co Ltd filed Critical Shibasoku Co Ltd
Priority to JP15835587A priority Critical patent/JPS643570A/en
Publication of JPS643570A publication Critical patent/JPS643570A/en
Pending legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)

Abstract

PURPOSE:To make digital conversion of a crest value with high accuracy by using a comparator having a high through rate and high-speed flip-flop. CONSTITUTION:For example, a '1' is set in the MSB of a register and other BITs are reset to '0' in a first stage. The presence or absence of the operation of the comparator 9 is stored in the flip-flop 10 and the result of the flip-flop 10 is read in the register 7 by the clock pulses between the ensuing stages so as to reset the flip-flop 10. The '1' is set in the MSB of the register 7 when the comparator 9 operates. The '1' is not set when the comparator does not operate. The result of the first stage is maintained in the MSB, the '1' is set in the BIT 2 and the BITs 3, 4 are held reset at the '0' in the next stage. The result of the BIT 2 is thereafter obtd. according to the presence or absence of the operation of the comparator 9 in the same manner as in the first stage. The same is executed with the BIT 3 in the ensuing stage and is further executed with the BIT 4 in the stage that follows said stage. The conversion of the crest value with the high accuracy is thus executed with the repeating waves of high frequencies.
JP15835587A 1987-06-25 1987-06-25 Crest value detector Pending JPS643570A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15835587A JPS643570A (en) 1987-06-25 1987-06-25 Crest value detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15835587A JPS643570A (en) 1987-06-25 1987-06-25 Crest value detector

Publications (1)

Publication Number Publication Date
JPS643570A true JPS643570A (en) 1989-01-09

Family

ID=15669851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15835587A Pending JPS643570A (en) 1987-06-25 1987-06-25 Crest value detector

Country Status (1)

Country Link
JP (1) JPS643570A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5866065A (en) * 1981-06-08 1983-04-20 テクトロニツクス・インコーポレイテツド Method of detecting signal
JPS58137769A (en) * 1982-02-10 1983-08-16 Matsushita Electric Ind Co Ltd Maximum value holding and alarming circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5866065A (en) * 1981-06-08 1983-04-20 テクトロニツクス・インコーポレイテツド Method of detecting signal
JPS58137769A (en) * 1982-02-10 1983-08-16 Matsushita Electric Ind Co Ltd Maximum value holding and alarming circuit

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