JPS6434037A - Loop back testing system in d channel communication protocol processing device - Google Patents

Loop back testing system in d channel communication protocol processing device

Info

Publication number
JPS6434037A
JPS6434037A JP62191086A JP19108687A JPS6434037A JP S6434037 A JPS6434037 A JP S6434037A JP 62191086 A JP62191086 A JP 62191086A JP 19108687 A JP19108687 A JP 19108687A JP S6434037 A JPS6434037 A JP S6434037A
Authority
JP
Japan
Prior art keywords
bit
protocol
address field
communication protocol
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62191086A
Other languages
Japanese (ja)
Inventor
Hidenori Hisamatsu
Noritaka Matsuura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62191086A priority Critical patent/JPS6434037A/en
Publication of JPS6434037A publication Critical patent/JPS6434037A/en
Pending legal-status Critical Current

Links

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  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To attain the normal action confirmation in accordance with a protocol on a D channel communication protocol by using a signal to invert the value of a CR bit in an address field included in a transmitting signal as a loop back signal. CONSTITUTION:By inverting the value of a CR bit in the address field of a transmitting frame, the normal action of a protocol processing can be executed even when all transmitting frames specified on a D channel communications protocol are loop-backed and received as they are. Namely, in the address field of a frame specified by the D channel communication protocol, a CR bit is included. The value of the CR bit included in the frame transmitted from a transmitting circuit 1 is inverted by a CR bit value inverting circuit 4 and received by a receiving circuit 7. Thus, the frame transmitted and received between a network side and a terminal side satisfies the protocol specification which unsymmetrical by the specification of the CR bit in an address field and a receiving and confirming can be executed.
JP62191086A 1987-07-29 1987-07-29 Loop back testing system in d channel communication protocol processing device Pending JPS6434037A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62191086A JPS6434037A (en) 1987-07-29 1987-07-29 Loop back testing system in d channel communication protocol processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62191086A JPS6434037A (en) 1987-07-29 1987-07-29 Loop back testing system in d channel communication protocol processing device

Publications (1)

Publication Number Publication Date
JPS6434037A true JPS6434037A (en) 1989-02-03

Family

ID=16268625

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62191086A Pending JPS6434037A (en) 1987-07-29 1987-07-29 Loop back testing system in d channel communication protocol processing device

Country Status (1)

Country Link
JP (1) JPS6434037A (en)

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