JPS643371U - - Google Patents
Info
- Publication number
- JPS643371U JPS643371U JP9677687U JP9677687U JPS643371U JP S643371 U JPS643371 U JP S643371U JP 9677687 U JP9677687 U JP 9677687U JP 9677687 U JP9677687 U JP 9677687U JP S643371 U JPS643371 U JP S643371U
- Authority
- JP
- Japan
- Prior art keywords
- display
- function
- frame memory
- reduction
- image
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002131 composite material Substances 0.000 claims description 3
- 230000006870 function Effects 0.000 claims 6
- 239000000203 mixture Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 238000000926 separation method Methods 0.000 description 2
Landscapes
- Studio Circuits (AREA)
Description
第１図は本考案の一実施例の全体構成図、第２
図は入力映像と出力合成画像の対応を示す図、第
３図は画像縮小原理図、第４図は複数画像を時分
割に選択し、フレームメモリーに記録する場合の
時分割動作の説明図、第５図はゲート回路ならび
にアドレス制御回路の動作説明図である。
１……映像入力端子、２……入力映像処理部、
３……Ｙ−Ｃ分離回路、４……同期分離回路、５
……Ａ−Ｄ変換器、６……縮小演算回路、７……
アドレス制御回路、８……ゲート回路、９……書
込制御回路、１０……フレームメモリー、１１…
…読出し制御回路、１２……ボーダー信号発生器
、１３……Ｄ−Ａ変換器、１４……テレビジヨン
カラーエンコーダー、１５……共通制御回路、１
６……映像出力端子、１７……カウンター回路、
１８……カウンター回路、１９……カウンター回
路、２０……デコーダー回路、２１……カウンタ
ー回路、２２……カウンター回路、２３……ＡＮ
Ｄ回路、２４……カウンター回路、２５……カウ
ンター回路、２６……カウンター回路、２７……
ＡＮＤ回路、２８……カウンター回路、２９……
書込禁止制御回路、３０……Ｖアドレス加算回路
、３１……Ｈアドレス加算回路、３２……アドレ
スゲート回路。
Figure 1 is an overall configuration diagram of one embodiment of the present invention, Figure 2
The figure shows the correspondence between the input video and the output composite image, Figure 3 is a diagram of the principle of image reduction, and Figure 4 is an explanatory diagram of the time-division operation when multiple images are selected in a time-division manner and recorded in a frame memory. FIG. 5 is an explanatory diagram of the operation of the gate circuit and address control circuit. 1...Video input terminal, 2...Input video processing section,
3...Y-C separation circuit, 4...Synchronization separation circuit, 5
...A-D converter, 6...Reduction arithmetic circuit, 7...
Address control circuit, 8...gate circuit, 9...write control circuit, 10...frame memory, 11...
... Readout control circuit, 12 ... Border signal generator, 13 ... D-A converter, 14 ... Television color encoder, 15 ... Common control circuit, 1
6...Video output terminal, 17...Counter circuit,
18...Counter circuit, 19...Counter circuit, 20...Decoder circuit, 21...Counter circuit, 22...Counter circuit, 23...AN
D circuit, 24... Counter circuit, 25... Counter circuit, 26... Counter circuit, 27...
AND circuit, 28... Counter circuit, 29...
Write inhibit control circuit, 30...V address addition circuit, 31...H address addition circuit, 32...address gate circuit.
Claims (1)
異なつた画像内容のテレビジヨン動画像信号の画
像寸法を水平方向、垂直方向とも縮小し、一台の
表示モニター装置に同時に複数の動画像を格子状
に分割合成表示する装置において、夫々のテレビ
ジヨン入力信号の内から縮小用の特定画素を時分
割に選択する機能を有し、これら選択された信号
を予め決められた一画面表示用フレームメモリー
の表示領域に記録する場合夫々の入力信号のラス
ター表示位置を検出する機能を有し、これら表示
位置に対応するフレームメモリーの記録アドレス
に直接縮小用特定画素を記録する機能を有し、さ
らにフレームメモリー記録アドレスを分割ブロツ
ク単位で自由に可変する機能を有し、合成画面上
で夫々の入力信号に対応した縮小用画像の表示位
置をリアルタイムで移動表示する機能を有し、一
つの表示装置に分割合成画像を表示する複数画像
画面合成装置。 The image dimensions of a television moving image signal with a plurality of different image contents that are reproduced with independent synchronization phases are reduced in both the horizontal and vertical directions, and a plurality of moving images are displayed simultaneously on a single display monitor device in a grid pattern. A device that performs split composite display has a function of time-divisionally selecting specific pixels for reduction from among each television input signal, and displays these selected signals in a predetermined frame memory for single-screen display. When recording in an area, it has a function to detect the raster display position of each input signal, and has a function to directly record specific pixels for reduction at the frame memory recording address corresponding to these display positions, and also has a function to record specific pixels for reduction directly to the frame memory recording address corresponding to these display positions. It has a function to freely change the address in units of divided blocks, and a function to move and display the display position of the reduced image corresponding to each input signal on the composite screen in real time, and it can be divided and composited on a single display device. A multiple image screen composition device that displays images.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9677687U JPH0540618Y2 (en) | 1987-06-23 | 1987-06-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9677687U JPH0540618Y2 (en) | 1987-06-23 | 1987-06-23 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS643371U true JPS643371U (en) | 1989-01-10 |
| JPH0540618Y2 JPH0540618Y2 (en) | 1993-10-14 |
Family
ID=31321878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9677687U Expired - Lifetime JPH0540618Y2 (en) | 1987-06-23 | 1987-06-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0540618Y2 (en) |
-
1987
- 1987-06-23 JP JP9677687U patent/JPH0540618Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0540618Y2 (en) | 1993-10-14 |
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