JPS643342U - - Google Patents

Info

Publication number
JPS643342U
JPS643342U JP9728487U JP9728487U JPS643342U JP S643342 U JPS643342 U JP S643342U JP 9728487 U JP9728487 U JP 9728487U JP 9728487 U JP9728487 U JP 9728487U JP S643342 U JPS643342 U JP S643342U
Authority
JP
Japan
Prior art keywords
circuit
squelch
limit trigger
operation timing
added
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9728487U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9728487U priority Critical patent/JPS643342U/ja
Publication of JPS643342U publication Critical patent/JPS643342U/ja
Pending legal-status Critical Current

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  • Transceivers (AREA)
  • Noise Elimination (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の全体の構成を示すブロツク図
、第２図は本考案のスケルチ回路に付加した演算
回路の動作タイミングチヤート、第３図は従来の
回路例を示すブロツク図である。 １：高周波および中間周波増幅器、２：復調器
、３：スケルチ回路、４：低周波増幅器、５：ス
ピーカ、６：ノイズフイルタ、７：整流回路、８
：シユミツトトリガ回路、９：演算回路、１０：
スイツチ回路。 FIG. 1 is a block diagram showing the overall configuration of the present invention, FIG. 2 is an operation timing chart of an arithmetic circuit added to the squelch circuit of the present invention, and FIG. 3 is a block diagram showing an example of a conventional circuit. 1: High frequency and intermediate frequency amplifier, 2: Demodulator, 3: Squelch circuit, 4: Low frequency amplifier, 5: Speaker, 6: Noise filter, 7: Rectifier circuit, 8
: Schmitt trigger circuit, 9: Arithmetic circuit, 10:
switch circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ノイズフイルタ、整流回路、シユミツトトリガ
回路および音声ラインのスイツチ回路とを備えた
無線機のスケルチ回路において、前記シユミツト
トリガ回路の出力を受けて前記スイツチ回路の動
作タイミングを制御するための演算回路を付加し
たことを特徴とするスケルチ回路。 In a squelch circuit for a radio equipped with a noise filter, a rectifier circuit, a limit trigger circuit, and an audio line switch circuit, an arithmetic circuit is added for receiving the output of the limit trigger circuit and controlling the operation timing of the switch circuit. A squelch circuit featuring:
JP9728487U 1987-06-26 1987-06-26 Pending JPS643342U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9728487U JPS643342U (en) 1987-06-26 1987-06-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9728487U JPS643342U (en) 1987-06-26 1987-06-26

Publications (1)

Publication Number Publication Date
JPS643342U true JPS643342U (en) 1989-01-10

Family

ID=31322612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9728487U Pending JPS643342U (en) 1987-06-26 1987-06-26

Country Status (1)

Country Link
JP (1) JPS643342U (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6048624A (en) * 1983-08-29 1985-03-16 Fujitsu Ten Ltd Squelch control circuit
JPS6055739A (en) * 1983-09-06 1985-04-01 Anritsu Corp Noise muting circuit of fm demodulator
JPS6086923A (en) * 1983-10-18 1985-05-16 Matsushita Electric Ind Co Ltd Audio muting circuit
JPS6152032A (en) * 1984-08-21 1986-03-14 Clarion Co Ltd Muting circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6048624A (en) * 1983-08-29 1985-03-16 Fujitsu Ten Ltd Squelch control circuit
JPS6055739A (en) * 1983-09-06 1985-04-01 Anritsu Corp Noise muting circuit of fm demodulator
JPS6086923A (en) * 1983-10-18 1985-05-16 Matsushita Electric Ind Co Ltd Audio muting circuit
JPS6152032A (en) * 1984-08-21 1986-03-14 Clarion Co Ltd Muting circuit

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