JPS643335U - - Google Patents
Info
- Publication number
- JPS643335U JPS643335U JP9776987U JP9776987U JPS643335U JP S643335 U JPS643335 U JP S643335U JP 9776987 U JP9776987 U JP 9776987U JP 9776987 U JP9776987 U JP 9776987U JP S643335 U JPS643335 U JP S643335U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- switch
- capacitor
- output circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims 4
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案の一実施例による二線式電子ス
イツチの構成を示す回路図、第２図はその動作時
の各部の波形を示す波形図である。
１，２……端子、３……出力回路、４……電源
回路、５……電子スイツチ主回路、６……遅延回
路、７……比較器、１１……負荷、１２……電源
、Ｔｒ１……トランジスタ（スイツチング素子）
。
FIG. 1 is a circuit diagram showing the configuration of a two-wire electronic switch according to an embodiment of the present invention, and FIG. 2 is a waveform diagram showing waveforms of various parts during operation. 1, 2... terminal, 3... output circuit, 4... power supply circuit, 5... electronic switch main circuit, 6... delay circuit, 7... comparator, 11... load, 12... power supply, Tr1 ...transistor (switching element)
.
Claims (1)
両端に設けられその間を開閉する出力回路と、 外部の変化を検出して前記出力回路を駆動する
スイツチ主回路と、 前記出力回路に並列に接続され、前記スイツチ
主回路に定電圧を供給する電源回路と、を有する
二線式電子スイツチにおいて、 前記スイツチ主回路の出力端と前記出力回路と
の間に接続され、その出力を所定時間遅延させる
遅延回路を有し、該遅延回路は、 前記電源回路の両端間に接続された抵抗及びコ
ンデンサの直列回路と、 前記スイツチ主回路の出力端に制御入力端が接
続され前記出力回路を開放するスイツチ出力によ
つて前記コンデンサを充電すべく制御し、前記出
力回路を閉成するスイツチ主回路のスイツチ出力
によつて前記コンデンサを放電すべく制御するス
イツチング素子と、 前記コンデンサの端子電圧が与えられ基準電圧
との比較により前記出力回路に制御信号を与える
比較器と、を有するものであることを特徴とする
二線式電子スイツチ。[Claims for Utility Model Registration] An output circuit that is provided at both ends of a pair of terminals to which a load and a power source are connected in series and opens and closes between them, and a main switch circuit that detects external changes and drives the output circuit. , a power supply circuit connected in parallel to the output circuit and supplying a constant voltage to the switch main circuit; has a delay circuit that delays its output for a predetermined period of time, and the delay circuit includes: a series circuit of a resistor and a capacitor connected across the power supply circuit; and a control input terminal connected to the output terminal of the switch main circuit. a switching element configured to control the capacitor to be charged by a switch output that opens the output circuit, and to discharge the capacitor by a switch output of a switch main circuit that closes the output circuit; 1. A two-wire electronic switch comprising: a comparator that receives a terminal voltage of a capacitor and provides a control signal to the output circuit by comparing it with a reference voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9776987U JPH0537552Y2 (en) | 1987-06-24 | 1987-06-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9776987U JPH0537552Y2 (en) | 1987-06-24 | 1987-06-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS643335U true JPS643335U (en) | 1989-01-10 |
| JPH0537552Y2 JPH0537552Y2 (en) | 1993-09-22 |
Family
ID=31323460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9776987U Expired - Lifetime JPH0537552Y2 (en) | 1987-06-24 | 1987-06-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0537552Y2 (en) |
-
1987
- 1987-06-24 JP JP9776987U patent/JPH0537552Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0537552Y2 (en) | 1993-09-22 |
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