JPS6432487A - Random access memory - Google Patents

Random access memory

Info

Publication number
JPS6432487A
JPS6432487A JP62187958A JP18795887A JPS6432487A JP S6432487 A JPS6432487 A JP S6432487A JP 62187958 A JP62187958 A JP 62187958A JP 18795887 A JP18795887 A JP 18795887A JP S6432487 A JPS6432487 A JP S6432487A
Authority
JP
Japan
Prior art keywords
row
circuits
piece
accordance
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62187958A
Other languages
Japanese (ja)
Inventor
Tsunenori Umeki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62187958A priority Critical patent/JPS6432487A/en
Priority to US07/194,707 priority patent/US4931999A/en
Publication of JPS6432487A publication Critical patent/JPS6432487A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the processing efficiency by increasing a row address decoder in accordance with a row output circuit provided by one piece or more. CONSTITUTION:Row I/O circuits 4, 8 being row output circuits are provided by one piece or more, and also, in accordance with the row output circuits 4, 8, row address decoders 3, 7 are increased. Accordingly, when one piece of word line in a memory cell array 1 has been selected by an address decoder 2, a data of (b) pieces of memory cells whose word lines are common are inputted to each of the row I/O circuits 4, 8. In such a way, by changing an address signal inputted to the row address decoders 3, 7 corresponding to the row I/O circuits 4, 8, data whose addresses are different are selected simultaneously and outputted, and an equivalent operation to an access to a RAM at a high speed is obtained, and a write operation is also executed in the same way.
JP62187958A 1987-07-27 1987-07-27 Random access memory Pending JPS6432487A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP62187958A JPS6432487A (en) 1987-07-27 1987-07-27 Random access memory
US07/194,707 US4931999A (en) 1987-07-27 1988-05-17 Access circuit for a semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62187958A JPS6432487A (en) 1987-07-27 1987-07-27 Random access memory

Publications (1)

Publication Number Publication Date
JPS6432487A true JPS6432487A (en) 1989-02-02

Family

ID=16215142

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62187958A Pending JPS6432487A (en) 1987-07-27 1987-07-27 Random access memory

Country Status (1)

Country Link
JP (1) JPS6432487A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04139695A (en) * 1990-09-30 1992-05-13 Nec Corp Semiconductor memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04139695A (en) * 1990-09-30 1992-05-13 Nec Corp Semiconductor memory

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