JPS6432296A - Driving of color flat panel display - Google Patents

Driving of color flat panel display

Info

Publication number
JPS6432296A
JPS6432296A JP18802087A JP18802087A JPS6432296A JP S6432296 A JPS6432296 A JP S6432296A JP 18802087 A JP18802087 A JP 18802087A JP 18802087 A JP18802087 A JP 18802087A JP S6432296 A JPS6432296 A JP S6432296A
Authority
JP
Japan
Prior art keywords
dot
display
line
display mode
color
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18802087A
Other languages
Japanese (ja)
Inventor
Eiji Imaizumi
Shozo Takamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP18802087A priority Critical patent/JPS6432296A/en
Publication of JPS6432296A publication Critical patent/JPS6432296A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To facilitate character and graphic display by making use of a first display mode for displaying with three color display dot for each line and a second display mode for displaying one pixel through the combination of each color display dot of odd numbered lines and even numbered lines where resolution is required in the horizontal direction. CONSTITUTION: Red, green and blue color display dot R, G, B are successively arranged for each line in the color liquid crystal display panel 10 of a color flat display, with the dot R, G, B successively arranged in the odd numbered line L1 , L3 .... In addition, for each even numbered line, L2 , L4 ..., the dot R, G, B are arranged by shifting 1.5 pitch assuming one dot width as one pitch. With a scanning circuit 14 and hold circuit 16 connected to this panel 10, it is controlled by a display control circuit 12. Then, the first display mode that displays one pixel through the set of dot R, G, B of the same line is set, by a display mode changeover switch 11, as is the second display mode that displays one pixel through the combination of each dot R, G, B of the odd numbered lines and even numbered lines.
JP18802087A 1987-07-28 1987-07-28 Driving of color flat panel display Pending JPS6432296A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18802087A JPS6432296A (en) 1987-07-28 1987-07-28 Driving of color flat panel display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18802087A JPS6432296A (en) 1987-07-28 1987-07-28 Driving of color flat panel display

Publications (1)

Publication Number Publication Date
JPS6432296A true JPS6432296A (en) 1989-02-02

Family

ID=16216256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18802087A Pending JPS6432296A (en) 1987-07-28 1987-07-28 Driving of color flat panel display

Country Status (1)

Country Link
JP (1) JPS6432296A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100490391B1 (en) * 1998-06-11 2005-08-01 삼성전자주식회사 Video Mode Control Device and Method of Computer with L.C.D

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100490391B1 (en) * 1998-06-11 2005-08-01 삼성전자주식회사 Video Mode Control Device and Method of Computer with L.C.D

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