JPS643213U - - Google Patents

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Publication number
JPS643213U
JPS643213U JP9389987U JP9389987U JPS643213U JP S643213 U JPS643213 U JP S643213U JP 9389987 U JP9389987 U JP 9389987U JP 9389987 U JP9389987 U JP 9389987U JP S643213 U JPS643213 U JP S643213U
Authority
JP
Japan
Prior art keywords
common potential
series
output terminal
input terminal
series resistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9389987U
Other languages
Japanese (ja)
Other versions
JPH0513060Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9389987U priority Critical patent/JPH0513060Y2/ja
Publication of JPS643213U publication Critical patent/JPS643213U/ja
Application granted granted Critical
Publication of JPH0513060Y2 publication Critical patent/JPH0513060Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例を示す接続図、第
2図はこの考案の具体的な回路構造を説明するた
めの平面図、第3図はその側面図、第4図はこの
考案による回路構造の減衰量の周波数特性を示す
グラフ、第5図は従来の減衰器の構造を説明する
ための接続図、第6図は従来の減衰器の減衰量の
周波数特性を示すグラフである。 1:入力端子、2:出力端子、3A,3B:直
列抵抗器、4:共通電位点、5,6:並列抵抗器
、7A,7B:直列抵抗器に寄生する浮遊容量、
8:並列抵抗器に寄生する浮遊容量。
Fig. 1 is a connection diagram showing an embodiment of this invention, Fig. 2 is a plan view for explaining the specific circuit structure of this invention, Fig. 3 is a side view thereof, and Fig. 4 is based on this invention. FIG. 5 is a connection diagram for explaining the structure of a conventional attenuator, and FIG. 6 is a graph showing the frequency characteristics of attenuation of a conventional attenuator. 1: input terminal, 2: output terminal, 3A, 3B: series resistor, 4: common potential point, 5, 6: parallel resistor, 7A, 7B: stray capacitance parasitic to series resistor,
8: Stray capacitance parasitic to the parallel resistor.

Claims (1)

【実用新案登録請求の範囲】 A 入力端子と出力端子との間に直列接続した複
数の直列抵抗器と、 B この直列抵抗器の各接続点と共通電位との間
に形成した静電容量と、 C 入力端子及び出力端子のそれぞれと共通電位
との間に接続した並列抵抗器と、 から成る高周波減衰器。
[Scope of Claim for Utility Model Registration] A. A plurality of series resistors connected in series between an input terminal and an output terminal; B. A capacitance formed between each connection point of the series resistors and a common potential. , C A high-frequency attenuator consisting of a parallel resistor connected between each of the input terminal and the output terminal and a common potential.
JP9389987U 1987-06-17 1987-06-17 Expired - Lifetime JPH0513060Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9389987U JPH0513060Y2 (en) 1987-06-17 1987-06-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9389987U JPH0513060Y2 (en) 1987-06-17 1987-06-17

Publications (2)

Publication Number Publication Date
JPS643213U true JPS643213U (en) 1989-01-10
JPH0513060Y2 JPH0513060Y2 (en) 1993-04-06

Family

ID=31318377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9389987U Expired - Lifetime JPH0513060Y2 (en) 1987-06-17 1987-06-17

Country Status (1)

Country Link
JP (1) JPH0513060Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081523A (en) * 2005-09-12 2007-03-29 Hochiki Corp Gain control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081523A (en) * 2005-09-12 2007-03-29 Hochiki Corp Gain control circuit

Also Published As

Publication number Publication date
JPH0513060Y2 (en) 1993-04-06

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