JPS643085B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal processing circuit that is effective for use in a device that records a color video signal such as a color television signal on a recording medium such as a magnetic tape or reproduces the same. .

Generally, when connecting a signal source with a DC component to multiple signal processing units such as an amplifier, the conventional method is to cut off the DC component using a capacitor and transmit only the AC component. Be taken. However, according to this method, multiple bias means are required to operate each of the multiple signal processing units, and the impedance of the coupling capacitor changes depending on the frequency, so the circuit network This causes deterioration of the overall frequency characteristics.

FIG. 1 shows an example of the above-mentioned circuit network, where e1 and e2 are alternating current signal sources and include direct current components E1 and E2. SW1 is a switch for selecting a signal source. In addition, C1, C2, C3 are coupling capacitors, R1, R1', R2, R2', R
3, R3', etc. are resistors constituting bias means, 1
1, 12, 13 are signal processing units, 11 ₀ , 12 ₀ , 1
₃₀ is the output end of each signal processing section, and EB is a DC power supply for bias.

Especially when the above circuit network is configured to drive multiple differential amplifiers in parallel, if there is a DC offset in the base bias of the two transistors that make up the differential amplifier, the input The dynamic range gain becomes unstable, causing distortion of the output signal. Furthermore, as the number of differential amplifiers increases, more bias power supplies or bias means are required. Particularly when such a circuit network is integrated, there arises the disadvantage that the base bias of each differential amplifier varies due to variations in the values of the bias means, and the number of pins increases.

This invention was made in order to cope with the above-mentioned situation, and extracts only the DC component from a DC signal accompanied by a DC component using a filter means consisting of a resistor and a capacitor, and applies this DC component as a bias. This provides a simple and stable signal processing circuit that does not involve DC offset and is suitable for integration into an integrated circuit by using the input signal of multiple differential amplifiers so that the other AC components can be processed as they are. The purpose is to That is, assuming that the first and second alternating current signals are applied to a plurality of differential amplifier groups, the bias condition should not be changed even when either signal is applied, and the bias condition should not be changed when either signal is applied. In this case, the bias voltage for each differential amplifier is obtained from a common portion.

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 2, e1 is a first signal based on alternating current, and includes a first direct current component E1. This first signal e1 is supplied to one end of each of resistors R4 and R5. The other end of the resistor R5 is connected to the reference potential end via a bypass capacitor C4, and is also connected to the second buffer circuit 22. Further, the other end of the resistor R4 is connected to the first buffer circuit 21. Note that the first and second buffer circuits 21 and 22 are configured with emitter followers. Here, the resistor R4 is used to compensate for the offset caused by the resistor R5 that constitutes the low-pass filter, and the resistor R4 is used for offset compensation with respect to the input impedance of the buffer circuit.
If the impedance of R5 is sufficiently small, the resistor R4 may be omitted.

Next, the output terminal of the first buffer circuit 21 is
It is connected to the first input terminal a of the switch means SW2. This switch means SW2 is for selecting one of the first and second input terminals a and b, and its output terminal is connected to a plurality of differential amplifiers DA1, DA2...
It is connected to each first differential input terminal of DAn.
Further, the output terminal of the second buffer circuit 22 is
The differential amplifiers DA1, DA2...DAn are commonly connected to second differential input terminals thereof.

Furthermore, a second input terminal b of said switch means SW2
A second signal input terminal 23 is connected to the signal input terminal 23, and a second signal E2 of alternating current containing a predetermined direct current component E2 is transmitted to this signal input terminal 23 via a capacitor C5 for cutting direct current. are supplied. Further, the second input terminal b of the switch means SW2 is connected to the differential amplifier mentioned above via a load resistor R6.
It is connected to each second differential input terminal of DA1 to DAn. This resistor R6 is such that when the switch means SW2 is on the second input terminal b side, the AC component e2 supplied via the input terminal 23 is connected to each differential amplifier DA1 to
This prevents the signal from being supplied to the second differential input end of DAn, and allows it to be supplied only to the first differential input end. Note that OUT1 to OUTn are output terminals of each differential amplifier.

One embodiment of the present invention is constructed as described above, and its operation will be explained next. That is, according to the above circuit, an AC signal is input to the first differential input terminal side of the plurality of differential amplifiers, and a DC component included in the AC signal is input to the other second differential input terminal side. is supplied as a bias, and can eliminate DC offset between the first and second differential input terminals.

In other words, when the switch means SW2 selects the first input terminal a, the first
The signal e1 is supplied to each first differential input terminal of the plurality of differential amplifiers DA1 to DAn via the buffer circuit 21. On the other hand, this AC first signal e is filtered by a low-pass filter such as a resistor R5 and a capacitor C4.
1, the AC component is removed. The remaining DC component is then supplied as a bias to the second differential input terminals of the plurality of differential amplifiers DA1 to DAn through the buffer circuit 22. As a result, bias and input signals are supplied to the first and second differential input terminals of the plurality of differential amplifiers DA1 to DAn without causing DC offset.

Next, when the switch means SW2 selects the second input terminal b, the plurality of differential amplifiers DA1 to DAn connect the bias connection means with the bias voltage determined by the first signal e1 side. biased through. and multiple differential amplifiers DA
A second signal e2 is input to the first differential input terminals of D1 to DAn via a capacitor C5.

A basic embodiment of the invention is constructed as described above. When the switch means SW2 selects the second input terminal b, the input impedance of the plurality of differential amplifiers DA1 to DAn is set to the resistor R6.
If this cannot be ignored compared to the voltage drop caused by the resistor R6, a DC offset will occur in the differential input by the voltage drop caused by the resistor R6, so further improvements may be made as shown in FIG. 3 to eliminate this.

That is, the same parts as in FIG. 2 will be described with the same reference numerals. In this embodiment, a resistor R7 is connected between the output terminal of the first buffer circuit 21 and the first input terminal a of the switch means SW2. and a resistor R6 and a second
A resistor R8 is commonly provided between the connection point 24 of the buffer circuit 22 and the second input terminals of the plurality of differential amplifiers DA1 to DAn.

According to the embodiment of FIG. 3 above, to compensate for the DC offset of resistor R6, resistors R7 and R8 are
It has been established. Here, if the values of the resistor R4 and the resistor R5 are equal, and the voltage drops due to the buffer circuits 21 and 22 are also the same, the DC potentials of the outputs of the two buffer circuits 21 and 22 will be the same E _B . Also, the first of the plurality of differential amplifiers,
The input DC voltage at the second differential input terminal is E ₊ and E _- respectively.
Then, the following equation holds true in each switching state of the switch means SW2.

When the switch means SW2 selects the first input terminal a E ₊ =E _B −I _B1 ×R7 E _- =E _B −I _B2 ×R8 When the switch means SW2 selects the second input terminal B E ₊ =E _B −I _B1 ×R6 E ₋ =E _B −I _B2 ×R8 However, I _B1 and I _B2 are the sum of the base currents of one of the n differential amplifiers. It is assumed that R6, R7, and R8 also represent the values of resistors R6, R7, and R8, respectively.

As you can see from the above formula, the value of the resistance is R6=
If R7=R8, then E ₊ = _E- regardless of the switching of the switch means SW2. Furthermore, since E _B depends on the same voltage source even with power supply fluctuations and temperature changes, E ₊ and E _- fluctuate in the same way, making it possible to obtain an extremely stable differential output. Furthermore, since no capacitors are provided for the AC signal input lines for each input terminal of the multiple differential amplifiers, there is no inconvenience that the input impedance will change even if the frequency of the AC signal changes. .

Particularly when the above circuit is integrated, variations in device performance and resistance ratio can be kept small, and it is also extremely effective in reducing the number of pins. Furthermore, the present invention is not limited to the above-mentioned embodiment, and as shown in FIG. It has the same effect as the example. Also, the second
It is possible to connect not only the input of the AC signal e2 but also the third and fourth input signals to the AC line by the same means, and in this case, the number of input terminals of the switch means may be increased. This switching means may be a changeover switch using an electronic circuit,
It may be manual or mechanical. Note that the same parts as in FIG. 2 are given the same reference numerals, and the description thereof will be omitted.

Next, an example of application of the present invention will be described with reference to FIG. FIG. 5 shows a signal processing section for reproduction signals and recording signals of a video tape recorder.

In FIG. 5, 35 is a signal source, which produces a 688 KHz color signal reproduced from the magnetic tape in the reproduction mode, and a 3.58 MHz recorded color signal in the recording mode. This input color signal is input to automatic color control amplifier 36 via capacitor C10 and subjected to gain control. This automatic color control amplifier 3
The output of No. 6 is input to the base of transistor Q ₁ constituting the first buffer circuit via resistor R4. Further, the output of the automatic color control amplifier 36 is
The AC component is bypassed by being introduced into a low-pass filter of resistor R5 and capacitor C4, and the DC component is input to the base of transistor _Q2 constituting the second buffer circuit.

The collector of the transistor _Q2 is connected to the power supply line 37, and the emitter is connected to the emitter resistor R1.
0 to the reference potential line 38. Also, the emitter of this transistor _Q2 is
It is connected to each bias supply terminal of the differential amplifiers of the frequency conversion circuit 31 , the color signal amplifier 32 , the automatic phase detector 33 , and the automatic color control detector 34 .

Next, the collector of the transistor _Q1 is connected to the power supply line 37, and the emitter is connected to a reference potential line 38 via an emitter resistor R11. Furthermore, the emitter of the transistor _Q1 is connected to the signal input terminal of the frequency conversion circuit 31 , and is also connected to the first input terminal of the switching means SW2 via the resistor R7.

The frequency conversion circuit 31 includes transistors Q ₃ ,
It consists of a double-balanced differential amplifier consisting of Q ₄ , Q ₅ , Q ₆ , Q ₇ , and Q ₈ . By inputting a carrier for frequency conversion between the common bases of transistors Q ₅ , Q ₃ and Q ₆ , Q ₇ ,
It converts the frequency of the signal input to the base of transistor Q ₃ and obtains the output from the common collector of transistors Q ₆ and Q ₈ . Note that _I1 is a current source. Further, R14, R15, R16, and R17 are resistors.

Next, the color signal amplifier 32 will be explained. This is constituted by a differential amplifier circuit including transistors Q ₁₀ and Q ₁₁ . When an AC signal is input to the base of transistor _Q10 , it is amplified and output from the collector of transistor _Q11 . Note that _I2 is a current source, and R21, R22, and R23 are resistors.

Next, to explain the automatic phase detector 33 ,
This detector also has a gate section and a phase detection section using a differential amplifier circuit. i.e. transistor
_Q12 and _Q15 form a differential amplifier and the transistor
A color signal is input to the base of Q ₁₂ , but
Phase detection operation is obtained during the burst signal period. Transistors Q ₁₃ and Q ₁₄ are connected in parallel to Q ₁₂ and Q ₁₅ , respectively, and a burst gate pulse is supplied to their bases during the burst period. In addition, the upper stage transistors _Q16 to _Q19 form a double-balanced differential amplifier, and the transistors Q16 to Q19 form a double-balanced differential amplifier.
A 3.58MHz oscillation output for phase comparison is supplied to the bases of Q ₁₇ and Q ₁₈ . Then, the phase difference output is output from the collectors of transistors Q ₁₆ and Q ₁₈ ,
The signal is input to the reduction filter 41. The output of the automatic phase detector 33 detects the phase difference between the burst signal and the output of a 3.58 MHz oscillator oscillating within the video tape recorder. The output is therefore used as a frequency control signal for the oscillator to obtain stable color signal processing. Note that _I3 is a current source, and R25
is resistance. Further, the base of the transistor _Q15 is supplied with the DC bias from the reduction filter. Further, the common base of the transistors Q ₁₆ and Q ₁₉ is supplied with a bias from the DC power supply E _B.

Next, the automatic color control detector 34 will be explained. This detector has almost the same configuration as the automatic phase detector 33 described above, and the lower stage transistors Q ₂₁ to _{Q 24}
and upper stage transistors _Q25 to _Q28 . Then, a burst gate pulse is supplied to the bases of transistors Q ₂₂ and Q ₂₃ , and a burst signal is extracted from the color signal input to transistor Q ₂₁ , and transistors Q ₂₅ , Q ₂₆ , Q ₂₇ ,
Detected at Q ₂₈ part. Then, the output is derived from the common collector of transistors Q ₂₅ and Q ₂₇ ,
The signal is input to the reduction filter 42. The output of this reduction filter 42 is applied to the gain control terminal of the automatic color control amplifier 36. Note that I ₄ is a current source,
R26, R27, and R28 are resistors. Further, the base of the transistor _Q24 is supplied with the DC bias from the reduction filter described above. Further, the common base of transistors Q ₂₅ and Q ₂₈ is supplied with a bias from a DC power supply E _B.

In the signal processing circuit section of the video tape recorder described above, for example, in the recording mode, the switch means SW2 is switched to the first input terminal side.
Since it is in the recording mode, a 3.58 MHz band color signal for recording is input to the automatic color control amplifier 36. This signal is then converted by the frequency conversion circuit 31 into a low-frequency 688KHz color signal. In order to stabilize the 688KHz color signal for recording, the automatic color control amplifier 3
It is necessary to make the amplitude of the color signal (3.58 MHz) input to 6 stable. For this purpose, the output of the automatic color control detector 34 is fed back to the control end of the automatic color control amplifier 36 through a low-pass filter 42.

Next, in order to make the 688 KHz band color signal for recording more stable, it is necessary to stabilize the relative relationship between the carrier frequency for frequency conversion and the 3.58 MHz burst signal frequency. Therefore, by adding the detected voltage obtained in the automatic phase control detector 33 as a control signal to the 3.58MHz voltage controlled oscillator for creating the carrier, the phase relationship is also stabilized. .

Next, when the video tape recorder is in the playback mode, the switch means SW2 is switched to the second input end side. Furthermore, the reproduced color signal in the 688 MHz band is input to the automatic color control amplifier 36. This color signal is converted by a frequency conversion circuit 31 into a 3.58 MHz band color signal that can be reproduced by a normal television receiver.

The frequency-converted reproduced color signal (3.58 MHz) is input as a second signal source via a capacitor C5, and is amplified by the amplifier 32 and output as a reproduced color signal. In order to make the reproduced color signal (3.58MHz) stable, it is necessary to make the amplitude of the burst signal stable. For this purpose, a detection output is obtained in the automatic color control amplifier circuit 34 and is supplied to the control end of the automatic color control amplifier 36 through a low-pass filter 42.

Furthermore, in order to stabilize the reproduced color signal (3.58MHz), it is necessary to stabilize the relative frequency relationship between the carrier frequency input to the frequency conversion circuit 31 and the color signal. Therefore, the automatic phase control detector 33 compares the burst period of the reproduced color signal (3.58MHz) with the output frequency of the reference voltage controlled oscillator for creating the carrier, detects the phase error, and detects the phase error. The DC detection output is applied as a control signal to the control end of the voltage controlled oscillator.

The signal processing circuit section of the video tape recorder described above is one to which the present invention is applied, and when integrated into an integrated circuit, extremely stable operation can be obtained.
Enables high-quality signal processing with little DC offset.

As mentioned above, the signal processing circuit of the present invention has the following features:
a plurality of differential amplifiers each having a first and a second differential input terminal; a first signal source that outputs a signal in which a first AC signal e1 is superimposed on a predetermined DC potential; filter means (resistor R5, capacitor C4) for removing the alternating current signal component e1 from the output of the signal source and outputting a direct current potential equivalent to the direct current potential; first and second input terminals a, b and an output terminal; a switch means SW2 that selectively guides one of the signals supplied to the first and second input terminals to the output terminal; a second signal source that outputs the second AC signal e2; a first signal transmission path including a first buffer circuit 21 that supplies the output of the first signal source to a first input terminal a of the switch means SW2; C5
a second signal transmission line for supplying the output of the filter means to the second input terminal b of the switch means SW2 via a second buffer circuit 22; means for supplying the signal led to the output terminal of the switch means SW2 to a first differential input terminal of each of the differential amplifiers; a second differential input terminal of the switch means SW2;
and a coil 25 connected between the input terminal b of the differential amplifier and the second differential input terminal of each of the differential amplifiers.

Alternatively, a resistor R6 may be connected in place of the coil 25, and the output end of the buffer circuit 21 may be connected to the switch means SW2 via the resistor R7.
The connection point between the second buffer circuit 22 and the resistor R6 is connected to the second differential input terminal of each differential amplifier via a resistor R8, and each resistor R6, This is a configuration in which the values of R7 and R8 are equal.

As a result, this invention extracts only the DC component consisting of resistors, capacitors, etc. from an AC signal with DC components, uses this DC component as a bias, and subjects AC signals with other DC components as they are to signal processing. As an input signal for a differential amplifier, we can obtain a simple and stable circuit that does not involve DC offset and is suitable for integrated circuits with a small number of pins, and is also suitable for circuits that handle multiple input signals. A signal processing circuit can be provided.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the configuration of a conventional signal processing circuit, FIG. 2 is an explanatory diagram of the configuration of a signal processing circuit according to an embodiment of the present invention, and FIGS. 3 and 4 are respectively according to other embodiments of the invention. FIG. 5 is a specific circuit diagram of a signal processing circuit of a video tape recorder to which the present invention is applied. e1...first signal, R4-R8...resistance, C
4... Capacitor, SW2... Switch means, e
2...Second signal, DA1, DA2...DAn...Differential amplifier, 21, 22...Buffer circuit.

Claims (1)

[Claims] 1. A plurality of differential amplifiers each having a first and a second differential input terminal, and a first signal source that outputs a signal in which a first AC signal is superimposed on a predetermined DC potential. and filter means for removing the alternating current signal component from the output of the first signal source and outputting a direct current potential equivalent to the direct current potential, and a first input end, a second input end, and an output end. a switch means for selectively guiding one of the signals supplied to the first and second input terminals to the output terminal; a second signal source outputting the second AC signal; a first signal transmission line including a first buffer circuit that supplies the output of the first signal source to the first input end of the switch means; and the output of the second signal source to the switch via a capacitor. a second input terminal of the means;
a signal transmission line; means for supplying the output of the filter means to a second differential input terminal of each of the differential amplifiers via a second buffer circuit; and a signal guided to the output terminal of the switch means. means for supplying a first differential input terminal of each of said differential amplifiers to a first differential input terminal of said respective differential amplifier; A signal processing circuit characterized by comprising a chiyoke coil. 2 a plurality of differential amplifiers each having a first and a second differential input terminal; a first signal source that outputs a signal in which a first AC signal is superimposed on a predetermined DC potential; filter means for removing the alternating current signal component from the output of the signal source and outputting a direct current potential equivalent to the direct current potential; a first input end, a second input end, and an output end; a switch means for selectively guiding one of the signals supplied to the second input terminal to the output terminal; a second signal source outputting a second AC signal; and an output of the first signal source. a first signal transmission line that supplies the output of the second signal source to the first input terminal of the switch means via a first buffer circuit and a first resistor; the second input terminal of the
a signal transmission path, means for supplying the signal led to the output end of the switch means to a first differential input end of each of the differential amplifiers, and a means for supplying the output of the filter means via a second buffer circuit. and connecting one end of each of a second and third resistor having the same resistance value as the first resistor, and connecting the other end of the second resistor to a second differential input terminal of each of the differential amplifiers; The other end of the third resistor is connected to the second end of the switching means.
A signal processing circuit comprising means for connecting to an input end.