JPS643074B2 - - Google Patents
Info
- Publication number
- JPS643074B2 JPS643074B2 JP5714282A JP5714282A JPS643074B2 JP S643074 B2 JPS643074 B2 JP S643074B2 JP 5714282 A JP5714282 A JP 5714282A JP 5714282 A JP5714282 A JP 5714282A JP S643074 B2 JPS643074 B2 JP S643074B2
- Authority
- JP
- Japan
- Prior art keywords
- active layer
- semiconductor active
- narrow
- gate
- sides
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 10
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910000927 Ge alloy Inorganic materials 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
本発明は特にシヨツトキーバリア型電界効果ト
ランジスタの構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates in particular to the structure of a Schottky barrier field effect transistor.
シヨツトキーバリア型電界効果トランジスタは
種々のものが提案されているが、特にゲート電極
が有する抵抗成分が原因で充分にその特性を引き
出せないのが現状である。また、半導体チツプ上
に形成されたシヨツトキーバイア型電界効果トラ
ンジスタは電極形状に対称性がなく、容器や
MIC基板に実装する時、その方向をそろえなけ
ればならず、作業効率向上の障害となつていた。 Although various types of Schottky barrier field effect transistors have been proposed, the current situation is that their characteristics cannot be fully exploited, particularly due to the resistance component of the gate electrode. In addition, short-key via field effect transistors formed on semiconductor chips lack symmetry in the shape of their electrodes, and
When mounting on a MIC board, the direction had to be aligned, which was an obstacle to improving work efficiency.
本発明の目的は、電極の抵抗成分による影響を
受けがたく、容器やMIC基板への実装時にチツ
プの方向を容易に設定できる電界効果トランジス
タを提供することにある。 An object of the present invention is to provide a field effect transistor that is not easily affected by the resistance component of the electrodes and allows the direction of the chip to be easily set when mounted on a container or MIC board.
本発明によれば、高比抵抗層上に形成された半
導体活性層と、該半導体活性層に設けられた幅広
部および幅狭部を含む開孔と、該開孔の幅狭部を
横切つて半導体活性層に接するゲート電極部およ
びその幅狭部におけるゲート電極部の中央部から
両側の幅広部に延在する対称な形状を有する２つ
のゲート電極取り出し部を含むゲート電極と、該
ゲート電極を挟んで対向し、互いに対称な形状の
ソースおよびドレイン電極とを含む電界効果トラ
ンジスタを得る。 According to the present invention, a semiconductor active layer formed on a high resistivity layer, an opening including a wide portion and a narrow portion provided in the semiconductor active layer, and a hole crossing the narrow portion of the opening are provided. a gate electrode including a gate electrode portion in contact with a semiconductor active layer, and two gate electrode lead-out portions having a symmetrical shape extending from the center portion of the gate electrode portion in the narrow portion thereof to wide portions on both sides; A field effect transistor is obtained that includes a source electrode and a drain electrode that are symmetrical to each other and that face each other with the electrodes in between.
以下、本発明をデユアルゲート電界効果トラン
ジスタに適用して図面により詳細に説明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be explained in detail by applying it to a dual-gate field effect transistor with reference to the drawings.
第１図ａ〜ｇは本発明の一実施例によるデユア
ルゲート電界効果トランジスタをその製造工程順
に示す図で、同図ｃ，ｅおよびｇはそれぞれ同図
ｂ，ｄおよびｆのＡ−A′方向の断面図である。
クロムをドープした高抵抗例えば103Ω−cmの比
抵抗をもつ半絶縁性ガリウムヒ素基板１上に、不
純物として例えばシリコンを例えば、10×17cm−
３の濃度で含むｎ型ガリウムヒ素層２を例えば
0.3μの厚さでエピタキシヤル成長させる（第１図
ａ）。このウエハーを、写真食刻法を用いて、各
電極パツド部を絶縁するためにｎ型ガリウムヒ素
層の一部を、その厚み方向において半絶縁性ガリ
ウムヒ素基板に到達する迄、例えば、硫酸と過酸
化水素水と純水との混合液を用いて除去する（第
１図ｂ，ｃ）。これによつて、活性層２には幅広
部および幅狭部を有する開孔が設けられる。次に
写真食刻法を用いて、ソース電極パターン３およ
びドレイン電極パターン４を例えば真空蒸着法に
より形成する。例えば金ゲルマニウム合金を各電
極配置に相当する位置に被着させ、例えば水素雰
囲気中において400℃で熱処理することにより、
金ゲルマニウム合金はｎ型ガリウムヒ素層２とオ
ーミツク接触Ｕ、ソース電極パターン３およびド
レイン電極パターン４が得られる（第１図ｄ，
ｅ）。次に例えば、やはり写真食刻法を用いて第
一ゲートおよび第二ゲート用の金属として例えば
アルミニウムを例えば真空蒸着法によりガリウム
ヒ素上に被着し、第一ゲート電極パターン５０お
よび第二ゲート電極パターン６０を形成せしめる
（第１図ａ，ｂ）。各ゲート電極パターン５０，６
０は、チヤンネル領域をつくるゲート電極部５′
と電極取り出しのための電極取り出し部５″，
６″とを夫々有する。また、ゲート電極部５′，
６′は幅狭部を横切つて活性層２と接し、電極取
り出し部５″，６″は幅広部に設けられている。 1A to 1G are views showing a dual-gate field effect transistor according to an embodiment of the present invention in the order of its manufacturing process; FIGS. FIG.
On a semi-insulating gallium arsenide substrate 1 doped with chromium and having a specific resistance of, for example, 10 3 Ω-cm, silicon is added as an impurity, for example, 10 × 17 cm-
For example, an n-type gallium arsenide layer 2 containing a concentration of
It is grown epitaxially to a thickness of 0.3μ (Figure 1a). Using photolithography, a portion of the n-type gallium arsenide layer is removed using, for example, sulfuric acid, in the thickness direction until it reaches the semi-insulating gallium arsenide substrate in order to insulate each electrode pad. It is removed using a mixture of hydrogen peroxide and pure water (Figure 1 b, c). Thereby, the active layer 2 is provided with an opening having a wide part and a narrow part. Next, a source electrode pattern 3 and a drain electrode pattern 4 are formed using photolithography, for example, by vacuum evaporation. For example, by depositing a gold-germanium alloy at a position corresponding to each electrode arrangement and heat-treating it at 400°C in a hydrogen atmosphere, for example,
The gold-germanium alloy provides an ohmic contact U with the n-type gallium arsenide layer 2, a source electrode pattern 3, and a drain electrode pattern 4 (Fig. 1d,
e). Next, for example, aluminum as a metal for the first and second gates is deposited on the gallium arsenide by vacuum evaporation, also using photolithography, and the first gate electrode pattern 50 and the second gate electrode A pattern 60 is formed (FIGS. 1a and 1b). Each gate electrode pattern 50, 6
0 is a gate electrode portion 5' forming a channel region.
and an electrode take-out part 5″ for taking out the electrode,
6'', respectively.Furthermore, gate electrode portions 5',
6' is in contact with the active layer 2 across the narrow part, and the electrode lead-out parts 5'' and 6'' are provided in the wide part.
かかる構造によれば、製造工的には何らの増加
もなくゲート電極パターンの抵抗成分による影響
を防止できる。つまり、各電極取り出し部５″，
６″に印加されたゲート電圧は、ゲート電極部
５′，６′の中央部に印加され、そして両端に伝わ
る。よつて、両端での電圧降下は等しく、かつ小
さい。それ故、抵抗成分による影響は防止され
る。 According to this structure, the influence of the resistance component of the gate electrode pattern can be prevented without any increase in the manufacturing process. In other words, each electrode extraction portion 5'',
The gate voltage applied to 6'' is applied to the center of the gate electrode parts 5' and 6' and is transmitted to both ends. Therefore, the voltage drop at both ends is equal and small. Therefore, the voltage drop due to the resistance component Impact is prevented.
さらに、ソースとドレインおよび第１と第２ゲ
ートの各電極パターンが図面より明らかなように
対称となつている。よつて、ソースとドレイン、
第一ゲートと第二ゲートとを同時に各電極配置を
変更することなく、交換しうるから、特にデユア
ルゲート電界効果トランジスタの多様な性能に応
じて電極配置を多様化する必要がなく、従つて特
にMIC化する場合、その製造原価低減に極めて
有効である。また、個別半導体素子としても、特
定の位置および方向性をもたないため、容器に入
れて組立てる時の作業性が向上し、製造原価低減
にも役立つ。 Furthermore, the electrode patterns of the source and drain and the first and second gates are symmetrical, as is clear from the drawings. So, source and drain,
Since the first gate and the second gate can be replaced at the same time without changing each electrode arrangement, there is no need to diversify the electrode arrangement in accordance with the various performances of dual-gate field effect transistors. When converting to MIC, it is extremely effective in reducing manufacturing costs. Furthermore, since individual semiconductor elements do not have a specific position or direction, the workability when assembling them in a container is improved, which also helps to reduce manufacturing costs.
第１図ａ〜ｇは本発明の一実施例によるデユア
ルゲート電界効果トランジスタをその製造工程順
に示す図で、同図ｃ，ｅおよびｇはそれぞれ同図
ｂ，ｄおよびｆのＡ−A′方向の断面図である。
１……半絶縁性ガリウムヒ素基板、２……ｎ型
ガリウムヒ素活性層、３……ソース電極パター
ン、４……ドレイン電極パターン、５０……第一
ゲート電極パターン、６０……第二ゲート電極パ
ターン、５′，６′……ゲート電極部、５″，６″…
…電極取り出し部。
1A to 1G are views showing a dual-gate field effect transistor according to an embodiment of the present invention in the order of its manufacturing process; FIGS. FIG. DESCRIPTION OF SYMBOLS 1... Semi-insulating gallium arsenide substrate, 2... N-type gallium arsenide active layer, 3... Source electrode pattern, 4... Drain electrode pattern, 50... First gate electrode pattern, 60... Second gate electrode Pattern, 5', 6'...Gate electrode part, 5'', 6''...
...Electrode extraction part.
Claims (1)
該半導体活性層の内部に形成された幅狭の開孔
と、該半導体活性層の内部に前記幅狭の開孔に連
続してかつその両側に形成された第１および第２
の幅広の開孔と、前記幅狭の開孔からその両側の
前記半導体活性層上に互いに平行して延在する第
１および第２のゲート電極と、前記第１および第
２のゲート電極の各中央部にそれぞれ接続して、
前記第１および第２の幅広の開孔内にそれぞれ形
成された互いに対称な形状を有する第１および第
２のゲートボンデイングパツドと、前記幅狭の開
孔の両側の部分以外で該部分の一方の側の前記半
導体活性層に被着されたソース電極と、前記幅狭
の開孔の両側の部分以外で該部分の他方の側の前
記半導体活性層に被着された、前記ソース電極と
は対称な形状のドレイン電極とを含むことを特徴
とする電界効果トランジスタ。1 A semiconductor active layer formed on a high resistivity layer,
a narrow aperture formed inside the semiconductor active layer; and first and second first and second apertures formed in the semiconductor active layer adjacent to the narrow aperture and on both sides thereof.
a wide opening; first and second gate electrodes extending parallel to each other from the narrow opening onto the semiconductor active layer on both sides thereof; Connect to each center part,
first and second gate bonding pads having symmetrical shapes formed in the first and second wide openings, respectively; a source electrode deposited on the semiconductor active layer on one side; and a source electrode deposited on the semiconductor active layer on the other side of the narrow opening other than the portions on both sides of the narrow opening. A field effect transistor comprising a symmetrically shaped drain electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5714282A JPS57181170A (en) | 1982-04-05 | 1982-04-05 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5714282A JPS57181170A (en) | 1982-04-05 | 1982-04-05 | Field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57181170A JPS57181170A (en) | 1982-11-08 |
| JPS643074B2 true JPS643074B2 (en) | 1989-01-19 |
Family
ID=13047318
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5714282A Granted JPS57181170A (en) | 1982-04-05 | 1982-04-05 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57181170A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE34244E (en) * | 1982-10-15 | 1993-05-11 | Sigma Enterprises, Inc. | Multiline slot machine |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6130298Y2 (en) * | 1976-08-05 | 1986-09-05 |
-
1982
- 1982-04-05 JP JP5714282A patent/JPS57181170A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57181170A (en) | 1982-11-08 |
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