JPS6430326A - Digital phase synchronizing circuit - Google Patents

Digital phase synchronizing circuit

Info

Publication number
JPS6430326A
JPS6430326A JP62186997A JP18699787A JPS6430326A JP S6430326 A JPS6430326 A JP S6430326A JP 62186997 A JP62186997 A JP 62186997A JP 18699787 A JP18699787 A JP 18699787A JP S6430326 A JPS6430326 A JP S6430326A
Authority
JP
Japan
Prior art keywords
circuit
frequency
signal
phase synchronizing
dividing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62186997A
Other languages
Japanese (ja)
Inventor
Shinichi Nakamura
Naohiko Toyoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba AVE Co Ltd
Original Assignee
Toshiba Corp
Toshiba Audio Video Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Audio Video Engineering Co Ltd filed Critical Toshiba Corp
Priority to JP62186997A priority Critical patent/JPS6430326A/en
Publication of JPS6430326A publication Critical patent/JPS6430326A/en
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To obtain a stable multiple signal processing circuit without adjustment by digitizing a phase synchronizing circuit. CONSTITUTION:An analog digital converted input signal (synchronized frequency signal) A is supplied through a latch circuit 11 to a gate circuit 13, the output of the gate circuit 13 is integrated by an integrating circuit 14 and thus, amplitude information of 0 or 1 is obtained. By the amplitude information, the frequency-dividing ratio of a frequency-dividing circuit 7 to frequency-divide a reference signal B is controlled, and by using the output of the frequency- dividing circuit 17, the conducting timing signal of the gate circuit 13 is obtained. Thus, the stability of a phase synchronizing group is obtained, and the phase control with the accuracy finer than the sampling period of the input signal can be obtained.
JP62186997A 1987-07-27 1987-07-27 Digital phase synchronizing circuit Pending JPS6430326A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62186997A JPS6430326A (en) 1987-07-27 1987-07-27 Digital phase synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62186997A JPS6430326A (en) 1987-07-27 1987-07-27 Digital phase synchronizing circuit

Publications (1)

Publication Number Publication Date
JPS6430326A true JPS6430326A (en) 1989-02-01

Family

ID=16198397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62186997A Pending JPS6430326A (en) 1987-07-27 1987-07-27 Digital phase synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS6430326A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0470263A1 (en) * 1990-02-23 1992-02-12 Amada Company Limited Method and apparatus for measuring the angle of work

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0470263A1 (en) * 1990-02-23 1992-02-12 Amada Company Limited Method and apparatus for measuring the angle of work
EP0470263B1 (en) * 1990-02-23 1997-05-07 Amada Company Limited Method and apparatus for measuring the angle of work

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