JPS6432507A - Fm demodulation circuit - Google Patents

Fm demodulation circuit

Info

Publication number
JPS6432507A
JPS6432507A JP18801487A JP18801487A JPS6432507A JP S6432507 A JPS6432507 A JP S6432507A JP 18801487 A JP18801487 A JP 18801487A JP 18801487 A JP18801487 A JP 18801487A JP S6432507 A JPS6432507 A JP S6432507A
Authority
JP
Japan
Prior art keywords
signal
terminal
demodulation
sampling clock
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18801487A
Other languages
Japanese (ja)
Inventor
Akira Sogo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yamaha Corp
Original Assignee
Yamaha Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yamaha Corp filed Critical Yamaha Corp
Priority to JP18801487A priority Critical patent/JPS6432507A/en
Priority to US07/221,117 priority patent/US4884037A/en
Publication of JPS6432507A publication Critical patent/JPS6432507A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To attain stable operation and no adjustment and to improve the demodulation sensitivity by providing an A/D conversion section converting an input FM modulation signal into a digital signal with a prescribed timing, a differentiation means, and a means obtaining a demodulation signal from an output of a low-pass filter. CONSTITUTION:An FM demodulation signal entered from a terminal 10 is given to an A/D converter 11 converting the signal into a digital signal synchronously with the timing of a sampling clock supplied from a terminal 12. An output signal of the converter 11 enters an input terminal of an exclusive OR gate 15 together with a signal retarded by one sampling clock by a delay device 13 receiving also said output signal and the delay device 13 and the gate 15 form a differentiation circuit 16. An output signal Sc of the circuit 16 is given to a low-pass filter 3 and a demodulation signal is outputted from a terminal 19. The pulse width of the signal Sc is proper and requires no adjustment principally by selecting the period of the sampling clock to be 1/4 of that of an FM carrier and the period is also made stable with high accuracy.
JP18801487A 1987-07-28 1987-07-28 Fm demodulation circuit Pending JPS6432507A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP18801487A JPS6432507A (en) 1987-07-28 1987-07-28 Fm demodulation circuit
US07/221,117 US4884037A (en) 1987-07-28 1988-07-19 FM demodulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18801487A JPS6432507A (en) 1987-07-28 1987-07-28 Fm demodulation circuit

Publications (1)

Publication Number Publication Date
JPS6432507A true JPS6432507A (en) 1989-02-02

Family

ID=16216148

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18801487A Pending JPS6432507A (en) 1987-07-28 1987-07-28 Fm demodulation circuit

Country Status (1)

Country Link
JP (1) JPS6432507A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5910752A (en) * 1997-12-09 1999-06-08 Qualcomm Incorporated Frequency demodulator with resampled output

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5910752A (en) * 1997-12-09 1999-06-08 Qualcomm Incorporated Frequency demodulator with resampled output

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