JPS6429082A - Color saturation control circuit - Google Patents

Color saturation control circuit

Info

Publication number
JPS6429082A
JPS6429082A JP18425887A JP18425887A JPS6429082A JP S6429082 A JPS6429082 A JP S6429082A JP 18425887 A JP18425887 A JP 18425887A JP 18425887 A JP18425887 A JP 18425887A JP S6429082 A JPS6429082 A JP S6429082A
Authority
JP
Japan
Prior art keywords
signal
multiplier
circuit
amplification
gain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18425887A
Other languages
Japanese (ja)
Inventor
Kunitoshi Hisaoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP18425887A priority Critical patent/JPS6429082A/en
Publication of JPS6429082A publication Critical patent/JPS6429082A/en
Pending legal-status Critical Current

Links

Landscapes

  • Processing Of Color Television Signals (AREA)

Abstract

PURPOSE:To suppress the flickering of a screen or chrominance noise at the time of the application of a power source or the switching of a channel by enforcing the gain of amplification into a prescribed value when the level of a burst signal is too heigh or the gain of amplification is too small. CONSTITUTION:An output signal from a multiplier 1 is supplied to an AND circuit 2 to take out a burst signal. Thus obtained signal is supplied to a compa rator 10 via an absolute value circuit 3, an averaging circuit 4, an accumulation circuit 5, and a latch circuit, and the signal is compared with a reference level. In accordance with the comparison result, a signal representing the amplification gain of the multiplier 1 is adjusted by an adder 9, from which an output is supplied to the multiplier 1 via a delay element 8. To a comparator 15, a signal representing the amplification gain outputted from the delay element 8 is input ted, and when this signal exceeds a set value, a switch 17 interrupts an output signal from the multiplier 1.
JP18425887A 1987-07-23 1987-07-23 Color saturation control circuit Pending JPS6429082A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18425887A JPS6429082A (en) 1987-07-23 1987-07-23 Color saturation control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18425887A JPS6429082A (en) 1987-07-23 1987-07-23 Color saturation control circuit

Publications (1)

Publication Number Publication Date
JPS6429082A true JPS6429082A (en) 1989-01-31

Family

ID=16150166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18425887A Pending JPS6429082A (en) 1987-07-23 1987-07-23 Color saturation control circuit

Country Status (1)

Country Link
JP (1) JPS6429082A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100354627B1 (en) * 1993-03-17 2002-12-26 산요 덴키 가부시키가이샤 Television circuit using color burst signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100354627B1 (en) * 1993-03-17 2002-12-26 산요 덴키 가부시키가이샤 Television circuit using color burst signal

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