JPS5474667A - Level adjustment system - Google Patents
Level adjustment systemInfo
- Publication number
- JPS5474667A JPS5474667A JP14206677A JP14206677A JPS5474667A JP S5474667 A JPS5474667 A JP S5474667A JP 14206677 A JP14206677 A JP 14206677A JP 14206677 A JP14206677 A JP 14206677A JP S5474667 A JPS5474667 A JP S5474667A
- Authority
- JP
- Japan
- Prior art keywords
- decoder
- level adjustment
- fed
- digital signal
- attenuated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
PURPOSE: To preform level adjustment of analog input singal, by controlling the reference voltage of the local decoder digitally.
CONSTITUTION: When the attenuated data pulse is latched to the serial parallel conversion circuit 27 and is fed to the variable attenuator 26, the reference DC voltage from the reference voltage input terminal 23 is attenuated or amplified according to the numeric value, and it is fed to the decoder 21. The decoder 21 decodes the digital signal from the digital signal input terminals 16 to 20 and delivers it to the output terminal 22.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14206677A JPS5474667A (en) | 1977-11-26 | 1977-11-26 | Level adjustment system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14206677A JPS5474667A (en) | 1977-11-26 | 1977-11-26 | Level adjustment system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5474667A true JPS5474667A (en) | 1979-06-14 |
Family
ID=15306626
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14206677A Pending JPS5474667A (en) | 1977-11-26 | 1977-11-26 | Level adjustment system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5474667A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56102119A (en) * | 1980-01-21 | 1981-08-15 | Hitachi Ltd | Analog-to-digital converting circuit |
JPS59143420A (en) * | 1983-02-04 | 1984-08-17 | Victor Co Of Japan Ltd | Expanding device of resolution |
JPS59193618A (en) * | 1983-04-18 | 1984-11-02 | Hitachi Ltd | Digital-analog converting system |
JPS6184116A (en) * | 1984-09-24 | 1986-04-28 | テクトロニツクス・インコーポレイテツド | Method and circuit for controlling bias of digital-analog converter |
JPS62121845U (en) * | 1986-01-22 | 1987-08-03 |
-
1977
- 1977-11-26 JP JP14206677A patent/JPS5474667A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56102119A (en) * | 1980-01-21 | 1981-08-15 | Hitachi Ltd | Analog-to-digital converting circuit |
JPS6333740B2 (en) * | 1980-01-21 | 1988-07-06 | Hitachi Ltd | |
JPS59143420A (en) * | 1983-02-04 | 1984-08-17 | Victor Co Of Japan Ltd | Expanding device of resolution |
JPS59193618A (en) * | 1983-04-18 | 1984-11-02 | Hitachi Ltd | Digital-analog converting system |
JPS6184116A (en) * | 1984-09-24 | 1986-04-28 | テクトロニツクス・インコーポレイテツド | Method and circuit for controlling bias of digital-analog converter |
JPS62121845U (en) * | 1986-01-22 | 1987-08-03 |
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