JPS6429044A - Data switching channel system - Google Patents

Data switching channel system

Info

Publication number
JPS6429044A
JPS6429044A JP18457587A JP18457587A JPS6429044A JP S6429044 A JPS6429044 A JP S6429044A JP 18457587 A JP18457587 A JP 18457587A JP 18457587 A JP18457587 A JP 18457587A JP S6429044 A JPS6429044 A JP S6429044A
Authority
JP
Japan
Prior art keywords
switch
control bit
sdsw
data
given
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18457587A
Other languages
Japanese (ja)
Inventor
Yoshinori Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18457587A priority Critical patent/JPS6429044A/en
Publication of JPS6429044A publication Critical patent/JPS6429044A/en
Pending legal-status Critical Current

Links

Landscapes

  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To perform high-speed burst-like data switching without using a processor by adding a switch control bit to the head field of date, and controlling a multistage switch by using this control bit. CONSTITUTION:The data, to which the switch control bit is added at its head field, is inputted to ID1, ID1+1. In a switch control circuit SWC, block transfer data which is outputted through header processing circuits IH1-IH2 is given to a digital space division switch SDSW according to the detection output of the header processing circuits IH1-IH2 and the switch state signal of the switch element SE of a rear stage. The SDSW selects successively a destination channel by using the control bit. In this case, when the switch stage of the SDSW is in a busy state, the transfer data is stored once in buffers BUF1, BUF2, and after waiting an idle state, is given to the switch of the rear stage.
JP18457587A 1987-07-23 1987-07-23 Data switching channel system Pending JPS6429044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18457587A JPS6429044A (en) 1987-07-23 1987-07-23 Data switching channel system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18457587A JPS6429044A (en) 1987-07-23 1987-07-23 Data switching channel system

Publications (1)

Publication Number Publication Date
JPS6429044A true JPS6429044A (en) 1989-01-31

Family

ID=16155604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18457587A Pending JPS6429044A (en) 1987-07-23 1987-07-23 Data switching channel system

Country Status (1)

Country Link
JP (1) JPS6429044A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5940958A (en) * 1995-05-10 1999-08-24 Littlefuse, Inc. Method of manufacturing a PTC circuit protection device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5940958A (en) * 1995-05-10 1999-08-24 Littlefuse, Inc. Method of manufacturing a PTC circuit protection device

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