JPS6424578A - Image display - Google Patents

Image display

Info

Publication number
JPS6424578A
JPS6424578A JP18045087A JP18045087A JPS6424578A JP S6424578 A JPS6424578 A JP S6424578A JP 18045087 A JP18045087 A JP 18045087A JP 18045087 A JP18045087 A JP 18045087A JP S6424578 A JPS6424578 A JP S6424578A
Authority
JP
Japan
Prior art keywords
address
circuit
preparing
plural
memories
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18045087A
Other languages
Japanese (ja)
Inventor
Takayuki Tsuruki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP18045087A priority Critical patent/JPS6424578A/en
Publication of JPS6424578A publication Critical patent/JPS6424578A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To cause the small number of memories to operate at a high speed to be sufficient by coupling wholly and equally a RAM and a selecting circuit to constitute a memory circuit for input. CONSTITUTION:Since an A/D converted video signal is successively stored to an address shown by a writing address preparing circuit 10 for preparing the writing address to plural RAMs 11 in a storing circuit 2 for input and the number of the RAMs 11 is smaller than the number of divisions of an image screen 7, the data of the block of plural image screens are accumulated to one RAM. Next, the contents of the address shown by an address preparing circuit 12 for preparing the reading address are successively read, transferred to a storing circuit 5 for output, and thus, plural electron guns 6 are driven and a screen is light-emitted simultaneously at the position on plural image screens. Thus, the number of memories to operate at a high speed can be reduced.
JP18045087A 1987-07-20 1987-07-20 Image display Pending JPS6424578A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18045087A JPS6424578A (en) 1987-07-20 1987-07-20 Image display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18045087A JPS6424578A (en) 1987-07-20 1987-07-20 Image display

Publications (1)

Publication Number Publication Date
JPS6424578A true JPS6424578A (en) 1989-01-26

Family

ID=16083442

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18045087A Pending JPS6424578A (en) 1987-07-20 1987-07-20 Image display

Country Status (1)

Country Link
JP (1) JPS6424578A (en)

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