JPS6422181A - Magnified image displaying signal generator - Google Patents

Magnified image displaying signal generator

Info

Publication number
JPS6422181A
JPS6422181A JP17726587A JP17726587A JPS6422181A JP S6422181 A JPS6422181 A JP S6422181A JP 17726587 A JP17726587 A JP 17726587A JP 17726587 A JP17726587 A JP 17726587A JP S6422181 A JPS6422181 A JP S6422181A
Authority
JP
Japan
Prior art keywords
signal
image
supplied
memory means
synchronizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17726587A
Other languages
Japanese (ja)
Inventor
Hideo Nishijima
Michio Masuda
Chikayuki Okamoto
Hitoaki Owashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP17726587A priority Critical patent/JPS6422181A/en
Publication of JPS6422181A publication Critical patent/JPS6422181A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a device easy to use by magnifying one part of an input image signal, simultaneously reducing the input image signal, inserting the whole image to one part of a magnified image and displaying a mixed image signal. CONSTITUTION:When an image input signal 16 is supplied from an input terminal 1, the signal 16 is separated into a luminance signal Y and color difference signals (R-Y, B-Y) by an analog processing circuit 2 and supplied to an analog- digital converter 3 on a time division basis. Here, the output of the circuit 2 is converted into a digital signal and supplied to first and second memory means 4 and 12. Writing control parts 9 and 13 are controlled by a synchronizing separation circuit 8 by a synchronizing signal separated by the signal 16. Thus, the signal 16 is written on the prescribed address position of the memory means 4 and 12. On the other hand, the control of reading is executed by controlling the output timing from the memory means 4 and 12 in matching with a vertical and horizontal synchronizing signal generated by a synchronizing signal generating circuit 11 by reading control parts 10 and 14.
JP17726587A 1987-07-17 1987-07-17 Magnified image displaying signal generator Pending JPS6422181A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17726587A JPS6422181A (en) 1987-07-17 1987-07-17 Magnified image displaying signal generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17726587A JPS6422181A (en) 1987-07-17 1987-07-17 Magnified image displaying signal generator

Publications (1)

Publication Number Publication Date
JPS6422181A true JPS6422181A (en) 1989-01-25

Family

ID=16028038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17726587A Pending JPS6422181A (en) 1987-07-17 1987-07-17 Magnified image displaying signal generator

Country Status (1)

Country Link
JP (1) JPS6422181A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003055207A1 (en) * 2001-12-11 2003-07-03 Thomson Licensing S.A. Multiplexed analog-to-digital converter arrangement

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003055207A1 (en) * 2001-12-11 2003-07-03 Thomson Licensing S.A. Multiplexed analog-to-digital converter arrangement
US7321399B2 (en) 2001-12-11 2008-01-22 Thomson Licensing Multiplexed analog-to-digital converter arrangement

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