JPS6421766A - Phase difference setting device for write data - Google Patents

Phase difference setting device for write data

Info

Publication number
JPS6421766A
JPS6421766A JP17652287A JP17652287A JPS6421766A JP S6421766 A JPS6421766 A JP S6421766A JP 17652287 A JP17652287 A JP 17652287A JP 17652287 A JP17652287 A JP 17652287A JP S6421766 A JPS6421766 A JP S6421766A
Authority
JP
Japan
Prior art keywords
data
read
write
error rate
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17652287A
Other languages
Japanese (ja)
Inventor
Takao Suzuki
Toshio Ko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP17652287A priority Critical patent/JPS6421766A/en
Publication of JPS6421766A publication Critical patent/JPS6421766A/en
Pending legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To minimize an error rate by automatically setting the combination of EARLY data, ordinary data and LATE data at the time of data write, at an optimum condition in which the error rate is smallest at the time of read. CONSTITUTION:A data selecting means 3 transfers the EARLY data, the ordinary data or the LATE data through combination to a read/write part 4 while selecting them according to a selection signal, sent by a test executing means 7, and writes the data in a record carrier. The data is compared with the write data for test of a first storing means 5 by a comparing means 8, and a read error is detected. An optimum pattern setting means 10 confirms a switch pattern, in which the number of the error was least, based on the data, stored in a second storing means 9, and makes a switch pattern control means 6 set a switch circuit 2 at the switch pattern. Thus, the error rate at the time of the read can be minimized.
JP17652287A 1987-07-15 1987-07-15 Phase difference setting device for write data Pending JPS6421766A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17652287A JPS6421766A (en) 1987-07-15 1987-07-15 Phase difference setting device for write data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17652287A JPS6421766A (en) 1987-07-15 1987-07-15 Phase difference setting device for write data

Publications (1)

Publication Number Publication Date
JPS6421766A true JPS6421766A (en) 1989-01-25

Family

ID=16015091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17652287A Pending JPS6421766A (en) 1987-07-15 1987-07-15 Phase difference setting device for write data

Country Status (1)

Country Link
JP (1) JPS6421766A (en)

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