JPS6415470U - - Google Patents
Info
- Publication number
- JPS6415470U JPS6415470U JP10874587U JP10874587U JPS6415470U JP S6415470 U JPS6415470 U JP S6415470U JP 10874587 U JP10874587 U JP 10874587U JP 10874587 U JP10874587 U JP 10874587U JP S6415470 U JPS6415470 U JP S6415470U
- Authority
- JP
- Japan
- Prior art keywords
- video signal
- leading edge
- level
- gain switching
- edge level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 230000008054 signal transmission Effects 0.000 claims 3
- 230000005540 biological transmission Effects 0.000 claims 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 7
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
Landscapes
- Picture Signal Circuits (AREA)
- Television Receiver Circuits (AREA)
Description
第１図はこの考案の一実施例の構成を示す回路
図、第２図及び第３図は第１図に示す回路の動作
を説明するために示す信号波形図、第４図は第１
図に示す回路の効果を説明するために示す信号波
形図、第５図は第１図に示す回路の具体的構成の
一例を示す回路図、第６図は第５図に示す回路の
動作を説明するための等価回路を示す回路図、第
７図はこの考案の他の実施例の構成を示す回路図
、第８図は第７図に示す回路の動作を説明するた
めに示す信号波形図、第９図は従来の問題を説明
するために示す信号波形図である。
１１，２１……端子、１２，２０……増幅回路
、１３……伸長及び圧縮回路、１４……同期先端
レベル検出回路、１５……利得切換え位置算出回
路、１６……黒レベル制御回路、１７……バツフ
ア、１８……コントラスト調整回路、１９……直
流再生回路、２４……圧縮回路。
FIG. 1 is a circuit diagram showing the configuration of an embodiment of this invention, FIGS. 2 and 3 are signal waveform diagrams shown to explain the operation of the circuit shown in FIG.
5 is a circuit diagram showing an example of a specific configuration of the circuit shown in FIG. 1, and FIG. 6 is a signal waveform diagram shown to explain the effect of the circuit shown in FIG. FIG. 7 is a circuit diagram showing the configuration of another embodiment of the invention; FIG. 8 is a signal waveform diagram showing the operation of the circuit shown in FIG. 7. , FIG. 9 is a signal waveform diagram shown to explain the conventional problem. 11, 21... terminal, 12, 20... amplifier circuit, 13... expansion and compression circuit, 14... synchronization tip level detection circuit, 15... gain switching position calculation circuit, 16... black level control circuit, 17 ... Buffer, 18 ... Contrast adjustment circuit, 19 ... DC regeneration circuit, 24 ... Compression circuit.
Claims (1)
伝送手段と、 上記映像信号に含まれる同期信号の先端レベル
を検出する同期先端レベル検出手段と、 この同期先端レベル検出手段によつて検出され
た上記同期信号の先端レベルに従つて、上記映像
信号のペデスタルレベル近傍に於いて予め設定さ
れた利得切換え位置を算出する利得切換え位置算
出手段と、 この利得切換え位置算出手段によつて算出され
た上記利得切換え位置で上記映像信号伝送手段に
於ける上記映像信号の伝送利得を切換える伝送利
得切換え手段と、 上記映像信号伝送手段を通つた上記映像信号の
直流分を再生する直流再生手段と、 上記同期先端レベル検出手段で検出された同期
先端レベルが、上記映像信号による画像が明るい
ときのレベルであるとき、上記直流再生手段から
出力される上記映像信号の黒レベルをシフトする
黒レベルシフト手段とを具備したことを特徴とす
る画質補正回路。[Claims for Utility Model Registration] Video signal transmission means for transmitting a video signal that does not include a DC component; Synchronization leading edge level detection means for detecting the leading edge level of a synchronizing signal included in the video signal; and This synchronizing leading edge level detection gain switching position calculation means for calculating a preset gain switching position near the pedestal level of the video signal according to the leading edge level of the synchronization signal detected by the means; and the gain switching position calculation means transmission gain switching means for switching the transmission gain of the video signal in the video signal transmission means at the gain switching position calculated by; and reproducing the DC component of the video signal that has passed through the video signal transmission means. When the synchronization leading edge level detected by the DC reproduction means and the synchronization leading edge level detection means is a level at which the image by the video signal is bright, the black level of the video signal output from the DC reproduction means is shifted. An image quality correction circuit comprising a black level shift means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10874587U JPS6415470U (en) | 1987-07-15 | 1987-07-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10874587U JPS6415470U (en) | 1987-07-15 | 1987-07-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6415470U true JPS6415470U (en) | 1989-01-26 |
Family
ID=31344367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10874587U Pending JPS6415470U (en) | 1987-07-15 | 1987-07-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6415470U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0324772U (en) * | 1989-07-21 | 1991-03-14 | ||
| JPH07940U (en) * | 1993-06-11 | 1995-01-06 | 若井産業株式会社 | Parts feeder |
-
1987
- 1987-07-15 JP JP10874587U patent/JPS6415470U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0324772U (en) * | 1989-07-21 | 1991-03-14 | ||
| JPH07940U (en) * | 1993-06-11 | 1995-01-06 | 若井産業株式会社 | Parts feeder |
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