JPS6413746U - - Google Patents
Info
- Publication number
- JPS6413746U JPS6413746U JP1987110390U JP11039087U JPS6413746U JP S6413746 U JPS6413746 U JP S6413746U JP 1987110390 U JP1987110390 U JP 1987110390U JP 11039087 U JP11039087 U JP 11039087U JP S6413746 U JPS6413746 U JP S6413746U
- Authority
- JP
- Japan
- Prior art keywords
- housing
- conductive pattern
- transparent resin
- current limiting
- limiting resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Description
第１図は本考案に係る灯具の一実施例を示す一
部破断状態の平面図、第２図及び第３図は同実施
例の正面図及び側面図、第４図は同実施例におけ
るＬＥＤチツプの実装状態を示す正面図、第５図
は第４図の−線断面図、第６図は従来例を示
す一部破断状態の平面図である。
１……ハウジング、１Ａ……取付部、２……導
電パターン、３……ＬＥＤチツプ、４……金線、
５……透明樹脂、６……電流制限用抵抗、７……
ワイヤーハーネス、８……アウターレンズ。
Fig. 1 is a partially cutaway plan view showing an embodiment of the lamp according to the present invention, Figs. 2 and 3 are front and side views of the embodiment, and Fig. 4 is an LED in the embodiment. FIG. 5 is a sectional view taken along the line -- in FIG. 4, and FIG. 6 is a partially cutaway plan view showing a conventional example. 1... Housing, 1A... Mounting part, 2... Conductive pattern, 3... LED chip, 4... Gold wire,
5... Transparent resin, 6... Current limiting resistor, 7...
Wire harness, 8...outer lens.
Claims (1)
ンを形成して所要数のＬＥＤチツプ、電流制限用
抵抗、逆電圧保護ダイオードなどを装着するとと
もに、各ＬＥＤチツプの部分を透明樹脂でレンズ
作用を持つように被覆し、ハウジングの前面にア
ウターレンズを取付けたことを特徴とする灯具。 A conductive pattern of a predetermined shape is formed on the rear inner surface of the housing, and the required number of LED chips, current limiting resistor, reverse voltage protection diode, etc. are mounted, and each LED chip is made of transparent resin to act as a lens. A light fixture characterized by having an outer lens attached to the front of the housing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987110390U JPH0514529Y2 (en) | 1987-07-17 | 1987-07-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987110390U JPH0514529Y2 (en) | 1987-07-17 | 1987-07-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6413746U true JPS6413746U (en) | 1989-01-24 |
| JPH0514529Y2 JPH0514529Y2 (en) | 1993-04-19 |
Family
ID=31347503
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987110390U Expired - Lifetime JPH0514529Y2 (en) | 1987-07-17 | 1987-07-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0514529Y2 (en) |
-
1987
- 1987-07-17 JP JP1987110390U patent/JPH0514529Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0514529Y2 (en) | 1993-04-19 |