JPS641321A - Pulse generator - Google Patents

Pulse generator

Info

Publication number
JPS641321A
JPS641321A JP62157258A JP15725887A JPS641321A JP S641321 A JPS641321 A JP S641321A JP 62157258 A JP62157258 A JP 62157258A JP 15725887 A JP15725887 A JP 15725887A JP S641321 A JPS641321 A JP S641321A
Authority
JP
Japan
Prior art keywords
period
analog signals
timer
output
cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62157258A
Other languages
Japanese (ja)
Other versions
JPH011321A (en
Inventor
Toshiaki Baba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shimadzu Corp
Original Assignee
Shimadzu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shimadzu Corp filed Critical Shimadzu Corp
Priority to JP62-157258A priority Critical patent/JPH011321A/en
Priority claimed from JP62-157258A external-priority patent/JPH011321A/en
Publication of JPS641321A publication Critical patent/JPS641321A/en
Publication of JPH011321A publication Critical patent/JPH011321A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To output high-speed pulses of a frequency which is higher than an analog sampling cycle, by making the fetching period of analog signals and the period of output pulses independently from each other.
CONSTITUTION: A programmable timer 4 is provided with a timer II 4b, whose period is variably determined by a fixed timer I 4a which regulates the period of analog signals and inputted analog signals. Namely, the analog signals are fetched in the period regulated by a 1st timer 4a and a 2nd period is regulated by the 2nd timer 4b in accordance with the value of the analog signals whenever the analog signals are fetched. Furthermore, pulse signals are outputted from an output circuit in accordance with the 2nd period. Therefore, the output of a 2nd timer can be set to time-up frequently during the period of the 1st cycle. Accordingly, such high-speed pulse signals that numerous pulses can be outputted during a unit period can be outputted during the 1st cycle, namely, the sampling period of the analog signals.
COPYRIGHT: (C)1989,JPO&Japio
JP62-157258A 1987-06-24 pulse generator Pending JPH011321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62-157258A JPH011321A (en) 1987-06-24 pulse generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62-157258A JPH011321A (en) 1987-06-24 pulse generator

Publications (2)

Publication Number Publication Date
JPS641321A true JPS641321A (en) 1989-01-05
JPH011321A JPH011321A (en) 1989-01-05

Family

ID=

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008013023A1 (en) * 2006-07-24 2008-01-31 Oval Corporation Processing method in operation system, flow rate converter, and coriolis flow meter

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008013023A1 (en) * 2006-07-24 2008-01-31 Oval Corporation Processing method in operation system, flow rate converter, and coriolis flow meter
JP2008027263A (en) * 2006-07-24 2008-02-07 Oval Corp Processing method in arithmetic system, flow rate converter, and coriolis flowmeter
US8184017B2 (en) 2006-07-24 2012-05-22 Oval Corporation Processing method in operation system, flow rate converter, and coriolis flow meter

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