JPS6412350A - Disk cache control system - Google Patents

Disk cache control system

Info

Publication number
JPS6412350A
JPS6412350A JP62168260A JP16826087A JPS6412350A JP S6412350 A JPS6412350 A JP S6412350A JP 62168260 A JP62168260 A JP 62168260A JP 16826087 A JP16826087 A JP 16826087A JP S6412350 A JPS6412350 A JP S6412350A
Authority
JP
Japan
Prior art keywords
access
cache memory
memory
range
control system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62168260A
Other languages
Japanese (ja)
Inventor
Sukenao Tanigawa
Kenichi Abo
Toshiharu Oshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62168260A priority Critical patent/JPS6412350A/en
Publication of JPS6412350A publication Critical patent/JPS6412350A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To eliminate a wasteful staging time, by performing data transfer within the range of access from a disk cache memory to a main memory device in parallel wit a staging processing. CONSTITUTION:When no block including a required access range exists in a cache memory 1, the access range is direct memory access memory (DMA) - transferred from a disk device 3 to the cache memory 1. Afterwards, the DMA transfer of the block to the last by a data chain is performed, and also, the data transfer of the access range from the cache memory 1 to the main memory device 2 is performed by triggering interruption due to the generation of the data chain.
JP62168260A 1987-07-06 1987-07-06 Disk cache control system Pending JPS6412350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62168260A JPS6412350A (en) 1987-07-06 1987-07-06 Disk cache control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62168260A JPS6412350A (en) 1987-07-06 1987-07-06 Disk cache control system

Publications (1)

Publication Number Publication Date
JPS6412350A true JPS6412350A (en) 1989-01-17

Family

ID=15864712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62168260A Pending JPS6412350A (en) 1987-07-06 1987-07-06 Disk cache control system

Country Status (1)

Country Link
JP (1) JPS6412350A (en)

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