JPS641058B2 - - Google Patents

Info

Publication number
JPS641058B2
JPS641058B2 JP8253180A JP8253180A JPS641058B2 JP S641058 B2 JPS641058 B2 JP S641058B2 JP 8253180 A JP8253180 A JP 8253180A JP 8253180 A JP8253180 A JP 8253180A JP S641058 B2 JPS641058 B2 JP S641058B2
Authority
JP
Japan
Prior art keywords
stem
plating
nickel plating
lead
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP8253180A
Other languages
Japanese (ja)
Other versions
JPS577951A (en
Inventor
Shoei Ikemoto
Kotaro Ishibashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Components Co Ltd
Original Assignee
Toshiba Components Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Components Co Ltd filed Critical Toshiba Components Co Ltd
Priority to JP8253180A priority Critical patent/JPS577951A/en
Publication of JPS577951A publication Critical patent/JPS577951A/en
Publication of JPS641058B2 publication Critical patent/JPS641058B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4871Bases, plates or heatsinks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】 本発明は全面仕上げニツケル鍍金工程を要さな
い半導体装置用ステムの製造法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a stem for a semiconductor device that does not require a complete nickel plating process.

従来から半導体装置用ステムはリード線をステ
ム本体上に、ガラス融着をした后は、最終的に必
ず仕上げのニツケル鍍金を全面にわたつて、施す
ことを必要としていた。
Conventionally, stems for semiconductor devices have required final nickel plating to be applied over the entire surface of the stem body after the lead wires have been fused to the stem body.

もし、この全面にわたる仕上げニツケル鍍金を
施さない場合は、リード及びステム本体にFe.Ni
の地肌が露出し、そのために、これをそのまゝ使
用する時は、Al線、Au線をリードに接着する時
に、その接着性が悪く使用に耐えないものとして
信頼性に乏しく、不良品となつてしまう。それ
故、リード線をステム本体に、ガラス融着したの
ちに行うところの、最終仕上げニツケル鍍金とい
う工程は、どうしても省略できない重要工程とな
つていた。
If this entire surface is not finished with nickel plating, the lead and stem body should be coated with Fe.Ni.
The bare skin of the lead is exposed, and therefore, when used as is, when adhering the Al wire or Au wire to the lead, the adhesion is poor and it cannot withstand use, resulting in poor reliability and being considered a defective product. I get used to it. Therefore, the final step of nickel plating, which is performed after the lead wire is glass fused to the stem body, has become an important step that cannot be omitted.

本発明者等は、この半導体装置用ステムの製造
工程中不可欠とされているこの仕上げのニツケル
鍍金という工程を、全く省いてしまつても、その
方法で得られた製品が機能的にみて、従来から行
われている仕上げニツケル鍍金工程をほどこした
方法で得られた製品と比べて、何ら変りない半導
体装置用ステムを得ることのできる方法を開発し
た。
The present inventors believe that even if the finishing process of nickel plating, which is considered essential in the manufacturing process of semiconductor device stems, is completely omitted, the products obtained by this method will be functionally superior to those of conventional ones. We have developed a method that makes it possible to obtain stems for semiconductor devices that are no different from products obtained using the final nickel plating process used in the previous method.

本発明の目的は、このような方法を提供しよう
とするものである。
The object of the present invention is to provide such a method.

本発明に係る方法の要旨とする構成は、特許請
求の範囲に示す如くステム本体、リード等のステ
ムを構成する部品の夫々について、ガラス焼結前
に、これらの下地に銅鍍金とニツケル鍍金とを施
して表面に予め鍍金層を形成しておき、次にこれ
らをそのままガラスと同時に焼結することを特徴
とするものである。
The gist of the method according to the present invention is that, as shown in the claims, copper plating and nickel plating are applied to the base of each of the stem main body, lead, and other parts constituting the stem before glass sintering. This method is characterized in that a plating layer is preliminarily formed on the surface, and then this is sintered as it is at the same time as the glass.

この場合、ニツケル鍍金に先立ち銅鍍金を施す
ことにより、部品単体毎のニツケル鍍金の定着性
が向上する。また、銅鍍金を施すことはステムの
半田濡れ性が良好となり、さらにボンデイング性
の向上等の効果がある。
In this case, by applying copper plating prior to nickel plating, the fixation of the nickel plating on each component is improved. In addition, copper plating improves the solder wettability of the stem and has the effect of improving bonding properties.

次に本発明に係る方法の一実施例を、添付図面
を参照しながら説明する。
Next, an embodiment of the method according to the present invention will be described with reference to the accompanying drawings.

第1図は、半導体装置用ステムの平面図であ
り、図中1はステム本体、2はガラス孔、3はガ
ラス、及び4は接着用リードを夫々示す。第2図
は、第1図のA−A線断面図である。
FIG. 1 is a plan view of a stem for a semiconductor device, in which 1 indicates a stem body, 2 a glass hole, 3 a glass, and 4 an adhesive lead. FIG. 2 is a sectional view taken along line A--A in FIG. 1.

かかる半導体装置用ステムは、表面に鍍金層イ
が形成されているが、第3図及び第4図に示すよ
うに、ステム本体1、リード4というようにステ
ム構成部品単体毎に予め銅鍍金、及びニツケル鍍
金を施す。この場合は銅鍍金、ニツケル鍍金の順
序で鍍金をする。
Such a stem for a semiconductor device has a plating layer (A) formed on its surface, and as shown in FIGS. and nickel plating. In this case, plating is performed in the order of copper plating and nickel plating.

その後、これらを組立ててガラス焼結を行ない
上記の半導体装置用ステムを得る。
Thereafter, these are assembled and glass sintered to obtain the above-mentioned stem for a semiconductor device.

次に本発明に係る方法を用いることにより得ら
れる利点を述べると (1) ステムの仕上げの鍍金という工程を全面的に
省略できるために、その製造工程において時間
の短縮、人手の軽減、材料特に薬品の節約等、
経済面において顕著な効果が期待できる。
Next, the advantages obtained by using the method according to the present invention are as follows: (1) The process of finishing the stem with plating can be completely omitted, so in the manufacturing process, time and labor can be reduced, and materials, especially Savings on chemicals, etc.
Significant economic effects can be expected.

(2) 仕上げニツケル鍍金工程の全面廃止をした場
合は、リード線の曲りを惹起するというような
ことが一切無くなり、歩留り、作業性の点で大
巾な能率向上を期することができる。
(2) If the finishing nickel plating process is completely abolished, there will be no bending of the lead wires, and a significant improvement in efficiency can be expected in terms of yield and workability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る方法で得たステム本体1
の平面図で第2図は第1図のA−A線による切断
面図である。第3図は部品単体としてのステム本
体の全表面に鍍金層を形成せしめた状態を示す説
明図で第4図は部品単体としての接着用リードの
全表面に鍍金層を形成せしめた状態を示す同じく
説明図である。 1……ステム本体、2……ガラス孔、3……ガ
ラス、4……接着用リード、イ……鍍金層。
Figure 1 shows a stem body 1 obtained by the method according to the present invention.
FIG. 2 is a plan view of FIG. 2, which is a sectional view taken along line A--A in FIG. Fig. 3 is an explanatory diagram showing a state in which a plating layer is formed on the entire surface of the stem body as a single component, and Fig. 4 shows a state in which a plating layer is formed on the entire surface of the adhesive lead as a single component. It is also an explanatory diagram. 1...Stem body, 2...Glass hole, 3...Glass, 4...Adhesive lead, A...Plating layer.

Claims (1)

【特許請求の範囲】[Claims] 1 ステム本体1、リード4等のステムを構成す
る部品の夫々について、ガラス焼結前に、これら
の下地に銅鍍金とニツケル鍍金とを施して表面に
予め鍍金層イを形成しておき、次にこれらをその
ままガラス3と同時に焼結することを特徴とする
半導体装置用ステムの製造法。
1 Before glass sintering, copper plating and nickel plating are applied to the base of each of the parts constituting the stem, such as the stem body 1 and the lead 4, to form a plating layer A on the surface. A method for manufacturing a stem for a semiconductor device, characterized in that these are sintered as they are at the same time as the glass 3.
JP8253180A 1980-06-18 1980-06-18 Manufacture of stem for semiconductor device needing no whole surface finishing nickel plating process Granted JPS577951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8253180A JPS577951A (en) 1980-06-18 1980-06-18 Manufacture of stem for semiconductor device needing no whole surface finishing nickel plating process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8253180A JPS577951A (en) 1980-06-18 1980-06-18 Manufacture of stem for semiconductor device needing no whole surface finishing nickel plating process

Publications (2)

Publication Number Publication Date
JPS577951A JPS577951A (en) 1982-01-16
JPS641058B2 true JPS641058B2 (en) 1989-01-10

Family

ID=13777082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8253180A Granted JPS577951A (en) 1980-06-18 1980-06-18 Manufacture of stem for semiconductor device needing no whole surface finishing nickel plating process

Country Status (1)

Country Link
JP (1) JPS577951A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0293183U (en) * 1989-01-12 1990-07-24

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4734350A (en) * 1986-12-29 1988-03-29 Xerox Corporation Positively charged developer compositions with modified charge enhancing additives containing amino alcohols

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6041860B2 (en) * 1980-03-14 1985-09-19 日本電気ホームエレクトロニクス株式会社 Manufacturing method for airtight terminals

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0293183U (en) * 1989-01-12 1990-07-24

Also Published As

Publication number Publication date
JPS577951A (en) 1982-01-16

Similar Documents

Publication Publication Date Title
JPS60208847A (en) Heat resisting plastic ic
DE1564491A1 (en) Semiconductor electric device and method for manufacturing the same
JPH0249021B2 (en)
DE2314731B2 (en) Semiconductor arrangement with hump-like projections on contact pads and method for producing such a semiconductor arrangement
DE2643147A1 (en) SEMICONDUCTOR DIODE
DE19540306C1 (en) Prodn. of conductor frames for semiconductor components
JPS641058B2 (en)
JPS60189940A (en) Manufacture of resin seal type semiconductor device
DE3704200C2 (en)
DE1614761A1 (en) Process for the production of a grounded capsule base for semiconductor elements
JPS57114265A (en) Ic lead frame and transistor comb and manufacture thereof
JPS6156623B2 (en)
JPH03274755A (en) Resin-sealed semiconductor device and manufacture thereof
JPH01244653A (en) Semiconductor device
JPS588586B2 (en) Sealing method for semiconductor devices
JPS6032774Y2 (en) Stem for semiconductor devices
JP2537630B2 (en) Method for manufacturing semiconductor device
KR830002575B1 (en) Manufacturing method of hermetic terminal
JPS60236251A (en) Package for semiconductor device
JPS607491Y2 (en) semiconductor equipment
JPS633462B2 (en)
JPS6011645Y2 (en) Airtight enclosure for cold pressure welding
JPS5897851A (en) Manufacture of metallic part
JPS6032779Y2 (en) power transistor stem
JPS5814606Y2 (en) semiconductor equipment