JPS6399539A - Manufacture of resin-sealed semiconductor device - Google Patents
Manufacture of resin-sealed semiconductor deviceInfo
- Publication number
- JPS6399539A JPS6399539A JP26712486A JP26712486A JPS6399539A JP S6399539 A JPS6399539 A JP S6399539A JP 26712486 A JP26712486 A JP 26712486A JP 26712486 A JP26712486 A JP 26712486A JP S6399539 A JPS6399539 A JP S6399539A
- Authority
- JP
- Japan
- Prior art keywords
- mold
- substrate
- resin
- space
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000011347 resin Substances 0.000 claims abstract description 48
- 229920005989 resin Polymers 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000002347 injection Methods 0.000 claims abstract description 11
- 239000007924 injection Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 2
- 238000000465 moulding Methods 0.000 description 12
- 230000000694 effects Effects 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 239000010445 mica Substances 0.000 description 1
- 229910052618 mica group Inorganic materials 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Abstract
Description
本発明は、半導体素子を固着した金属基板がほぼ直方体
の樹脂層によりて被覆され、その際基板の反素子支持面
を覆う樹脂層は放熱効果を上げるために、素子を覆う樹
脂層に比して薄くされる樹脂封止半導体装置の製造方法
に関する。In the present invention, a metal substrate to which a semiconductor element is fixed is covered with a substantially rectangular resin layer, and in this case, the resin layer covering the surface of the substrate opposite to the element support is made smaller than the resin layer covering the element in order to improve the heat dissipation effect. The present invention relates to a method of manufacturing a resin-sealed semiconductor device that can be made thinner.
半導体素子を支持する金属基板を表面に露出させて樹脂
封止した半導体装置においては、接地された放熱体上に
絶縁して固定する場合は、基板と放熱体の間にマイカ等
の絶縁板を介挿させていた。
このような絶縁板の使用を不要にするため、放熱体に固
定される側にも基板上に絶縁層を設けた樹脂封止半導体
装置を第2図に示し、(alは外観図。
(b)は断面図である0図において、半導体チップ1は
支持基板としてのリードフレームのマウント部2にろう
付けられており、外部リード部21と導線3によって接
続され、外部リード部21を露出させ、取付孔8を有す
る樹脂層4によって封止されている。この際、樹脂層4
のチップ側の厚さd、に比して反対側の厚さd、は著し
く薄くされていて、この半導体装置を面5によって放熱
体上に固定した場合の放熱性を良くしである。しがし、
このような樹脂層4の成形のために、金型空間内にリー
ドフレームを支持し、マウント部21に垂直な金型面に
設けられたゲート6から樹脂を注入すると、層厚さの差
異により樹脂流れに及ぼす抵抗が異なり、樹脂は基板2
のチップ側の広い金型空間に入りやすく、厚さd、の樹
脂層が早(成形され、基板2の反チップ側の厚さd、の
樹脂層は遅く成形される。そして、この反チップ側にゲ
ート6から直接入る樹脂と基板2のチップ側の金型空間
から廻ってくる樹脂との合流点が反チップ側の金型空間
にできるため、金型空間内の空気が十分に抜は切らず、
樹脂層4内に気泡、ピンホールが発生する。この現象は
薄い樹脂層の厚さd2が薄いほど、また封止面積が大き
い程著しい。In a semiconductor device in which a metal substrate supporting a semiconductor element is exposed on the surface and sealed with resin, if it is insulated and fixed on a grounded heat sink, an insulating plate such as mica should be placed between the substrate and the heat sink. I was intervening. In order to eliminate the need for such an insulating plate, a resin-sealed semiconductor device in which an insulating layer is provided on the substrate on the side fixed to the heat sink is shown in Fig. 2 (al is an external view. (b) ) is a cross-sectional view of FIG. 0, a semiconductor chip 1 is brazed to a mounting portion 2 of a lead frame serving as a supporting substrate, and is connected to an external lead portion 21 by a conductive wire 3, with the external lead portion 21 exposed. It is sealed by a resin layer 4 having a mounting hole 8. At this time, the resin layer 4
The thickness d on the opposite side is significantly thinner than the thickness d on the chip side, which improves heat dissipation when this semiconductor device is fixed on a heat sink by the surface 5. Shigashi,
In order to mold such a resin layer 4, when a lead frame is supported in the mold space and resin is injected from the gate 6 provided on the mold surface perpendicular to the mount section 21, due to the difference in layer thickness. The resistance to the resin flow is different, and the resin is
The resin layer with a thickness of d is molded quickly, and the resin layer with a thickness of d on the anti-chip side of the substrate 2 is molded slowly. Since the resin entering directly from the gate 6 on the side and the resin coming from the mold space on the chip side of the substrate 2 meet in the mold space on the opposite chip side, the air in the mold space can be sufficiently removed. No cutting,
Bubbles and pinholes are generated in the resin layer 4. This phenomenon becomes more pronounced as the thickness d2 of the thin resin layer becomes smaller and as the sealing area becomes larger.
【発明の目的]
本発明は、上述の問題を解決し、基板の半導体素子側の
厚い樹脂層と反素子側の薄い樹脂層への成形速度の差異
と、それに基づいて発生する樹脂層中の気泡含有、ピン
ホールの発生を防ぐことのできる樹脂封止半導体装置の
製造方法を提供することを目的とする。
【発明の要点】
本発明は、樹脂をほぼ直方体の空間をもつ金型の基板面
に垂直な金型面の一つに基板の半導体素子側の金型空間
に対向して設けられた主注入口と、その金型面に主注入
口より近い側で、隣接する基板面に垂直な金型面に基板
の反素子側の金型空間に対向して設けられた補助注入口
とより注入するもので、これにより基板の反素子側の薄
い樹脂層への成形速度を素子側の厚い樹脂層の成形速度
に同調させることができるので上記の目的が達成される
。[Object of the invention] The present invention solves the above-mentioned problems, and solves the difference in molding speed between the thick resin layer on the semiconductor element side of the substrate and the thin resin layer on the opposite side, and the difference in molding speed in the resin layer that occurs based on the difference in molding speed. It is an object of the present invention to provide a method for manufacturing a resin-sealed semiconductor device that can prevent the inclusion of air bubbles and the generation of pinholes. [Summary of the Invention] The present invention is directed to a main mold which is provided on one of the mold surfaces perpendicular to the substrate surface of a mold having an approximately rectangular parallelepiped space, facing the mold space on the semiconductor element side of the substrate. Injection is performed by an inlet and an auxiliary injection port provided on a side of the mold surface closer to the main injection port and facing the mold space on the side opposite to the element on the mold surface perpendicular to the adjacent substrate surface. This allows the molding speed of the thin resin layer on the side opposite to the element of the substrate to be synchronized with the molding speed of the thick resin layer on the element side, thereby achieving the above object.
第1図は本発明の一実施例を示し、(a)は樹脂成形後
の平面図、(blはでき上がった半導体装置の断面図で
あり、第2図と共通の部分には同一の符号が付されてい
る。図から明らかなように、樹脂は主ランナ7に連通ず
る主ゲート6と、主ランナ7から分岐した補助ランナ7
1に連通し、主ゲート6に近い側の隣接金型内側面に設
けられた補助ゲート61から注入される。第1図中)か
ら分がるように、主ゲート6は基板2のチップ1側の厚
さd、の広い金型空間に向けられており、補助ゲート6
1は基板2の反チップ側の厚さd8の狭い金型空間に向
けられている。これらの主ゲート6および補助ゲート6
1から樹脂を注入すると、厚さd2の狭い金型空間には
、各々のゲートからの樹脂がそれぞれ扇状に広がりなが
ら充填されていく。従って主ゲート6と補助ゲート61
の位置関係で厚さの薄い金型空間に流入する樹脂は、そ
の空間中の空気を押し出す方向に向かって成形されてい
く。この成形速度を基板のチップ側の広い金型空間の成
形速度と同調を取るために、補助ランナ71に連通する
補助ゲートを複数設けてもよい。
第3図は、主ゲート6が基板2の外部リード部21と反
対側に設けられた実施例を示す。
補助ゲート61を主ゲート6から遠い側の隣接側金型側
面に設けると前述の空気押し出し効果が順調に生じない
。ただし、主ゲート6が金型側面の中央に設けられると
きには、何れの隣接金型側面に設けられてもよい。
第4図、第5図は主ゲート6を主ランナ7の矢印9で示
す樹脂圧入方向に見てすべて手前側にそれぞれ設け、ま
た補助ランナ71を矢印9で示す樹脂圧入方向に見て主
ゲート6よりすべて手前側にそれぞれ設けたもので、こ
れにより第1図、第3図の場合に比して補助ランナ71
の数は増すが各金型空間への注入圧力が上がると共に均
一化するため、各半導体装置の健全な樹脂層4の成形を
一様に行うことができる利点がある。FIG. 1 shows an embodiment of the present invention, (a) is a plan view after resin molding, (bl is a cross-sectional view of the completed semiconductor device, and parts common to those in FIG. 2 are denoted by the same reference numerals. As is clear from the figure, the resin is applied to the main gate 6 communicating with the main runner 7 and the auxiliary runner 7 branched from the main runner 7.
1, and is injected through an auxiliary gate 61 provided on the inner side of the adjacent mold on the side closer to the main gate 6. 1), the main gate 6 faces a wide mold space with a thickness d on the chip 1 side of the substrate 2, and the auxiliary gate 6
1 is directed toward a narrow mold space with a thickness d8 on the side opposite to the chip of the substrate 2. These main gate 6 and auxiliary gate 6
When resin is injected from step 1, the narrow mold space having a thickness d2 is filled with resin from each gate while spreading out in a fan shape. Therefore, the main gate 6 and the auxiliary gate 61
The resin that flows into the thin mold space due to the positional relationship is molded in a direction that pushes out the air in that space. In order to synchronize this molding speed with the molding speed of the wide mold space on the chip side of the substrate, a plurality of auxiliary gates communicating with the auxiliary runner 71 may be provided. FIG. 3 shows an embodiment in which the main gate 6 is provided on the side of the substrate 2 opposite to the external lead portion 21. In FIG. If the auxiliary gate 61 is provided on the side of the adjacent mold that is far from the main gate 6, the above-mentioned air extrusion effect will not occur smoothly. However, when the main gate 6 is provided at the center of the side surface of the mold, it may be provided on any adjacent side surface of the mold. 4 and 5, the main gates 6 are all provided on the front side of the main runner 7 when viewed in the resin press-fitting direction shown by the arrow 9, and the main gates are all provided when the auxiliary runner 71 is viewed in the resin press-fitting direction shown by the arrow 9. The auxiliary runners 71 are all provided on the front side of the runners 6 and 6, respectively.
Although the number of molds increases, the injection pressure into each mold space increases and becomes uniform, which has the advantage that a sound resin layer 4 of each semiconductor device can be uniformly molded.
本発明によれば、半導体素子を支持する基板の素子側の
厚い金型空間に向かう注入口のほかに、反素子側の薄い
金型空間に向かう注入口・を−っまたは複数設けて薄い
樹脂層の成形速度を任意に設定することにより、厚い樹
脂層の成形速度に同調させることが可能になる。この結
果、基板の前後からの樹脂層の合流が防止され、樹脂の
完全充填が行われて樹脂層の気泡含有、ピンホールの発
生が防止され、また樹脂の合流による外観不良もなくな
る。本発明は個別素子のチップを樹脂封止した半導体装
置に限らず、モノリシックICチップ。
ハイブリッドIC基板を単独にあるいは複合して封止し
た半導体装置の製造に対しても有効に適用できる。According to the present invention, in addition to the injection port directed to the thick mold space on the element side of the substrate that supports the semiconductor device, one or more injection ports directed to the thin mold space on the anti-device side are provided to inject thin resin. By arbitrarily setting the molding speed of the layer, it becomes possible to synchronize the molding speed of a thick resin layer. As a result, the resin layers from the front and back of the substrate are prevented from merging, the resin is completely filled, and the resin layer is prevented from containing bubbles and pinholes, and the appearance defects due to the merging of the resins are also eliminated. The present invention is not limited to semiconductor devices in which individual element chips are sealed with resin, but also applies to monolithic IC chips. It can also be effectively applied to the manufacture of semiconductor devices in which hybrid IC substrates are sealed singly or in combination.
第1図は本発明の一実施例を示し、fa)は樹脂成形後
の平面図、(b)はでき上がった半導体装置の断面図、
第2図は従来の樹脂封止半導体装置を示し、(a)は斜
視図、(b)は断面図、第3図は本発明の異なる実施例
を示し、(a)は樹脂成形後の平面図、 (blはでき
上がった半導体装置の断面図、第4図、第5図はそれぞ
れ本発明のさらに異なる実施例の樹脂成形後の平面図で
ある。
1:半導体チップ、2:基板、21:外部リード、4:
樹脂層、6:主ゲート、61:補助ゲート、7:主ラン
ナ、71:補助ランナ。
1N開昭63−99539(4)
第4図
7オ〜六不=
・−ト←=FIG. 1 shows an embodiment of the present invention, fa) is a plan view after resin molding, (b) is a cross-sectional view of the completed semiconductor device,
FIG. 2 shows a conventional resin-sealed semiconductor device, (a) is a perspective view, (b) is a sectional view, and FIG. 3 is a different embodiment of the present invention, (a) is a plan view after resin molding. 1: Semiconductor chip, 2: Substrate, 21: External lead, 4:
Resin layer, 6: main gate, 61: auxiliary gate, 7: main runner, 71: auxiliary runner. 1N Kaisho 63-99539 (4) Fig. 4 7O~Rokufu = ・-T←=
Claims (1)
間内に支持し、樹脂を注入して基板の素子側に厚い樹脂
層、基板の反素子側に薄い樹脂層を成形する際に、基板
面に垂直な金型面の一つに基板の素子側の金型空間に対
向して設けられた主注入口と、前記金型面に主注入口よ
り近い側で、隣接する基板面に垂直な金型面に基板の反
素子側の金型空間に対向して設けられた補助注入口とよ
り樹脂を注入することを特徴とする樹脂封止半導体装置
の製造方法。1) When supporting a substrate on which a semiconductor element is fixed in a nearly rectangular parallelepiped space of a mold and injecting resin to form a thick resin layer on the element side of the substrate and a thin resin layer on the opposite side of the substrate, A main injection port is provided on one of the mold surfaces perpendicular to the substrate surface, facing the mold space on the element side of the substrate, and a main injection port is provided on the adjacent substrate surface on the side closer to the mold surface than the main injection port. A method for manufacturing a resin-sealed semiconductor device, characterized in that resin is injected through an auxiliary injection port provided on a vertical mold surface facing a mold space on the side opposite to an element of a substrate.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61-129927 | 1986-06-04 | ||
JP12992786 | 1986-06-04 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6399539A true JPS6399539A (en) | 1988-04-30 |
Family
ID=15021855
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26712486A Pending JPS6399539A (en) | 1986-06-04 | 1986-11-10 | Manufacture of resin-sealed semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6399539A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5368805A (en) * | 1992-03-24 | 1994-11-29 | Fuji Electric Co., Ltd. | Method for producing resin sealed type semiconductor device |
-
1986
- 1986-11-10 JP JP26712486A patent/JPS6399539A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5368805A (en) * | 1992-03-24 | 1994-11-29 | Fuji Electric Co., Ltd. | Method for producing resin sealed type semiconductor device |
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