JPS63992B2 - - Google Patents
Info
- Publication number
- JPS63992B2 JPS63992B2 JP57105961A JP10596182A JPS63992B2 JP S63992 B2 JPS63992 B2 JP S63992B2 JP 57105961 A JP57105961 A JP 57105961A JP 10596182 A JP10596182 A JP 10596182A JP S63992 B2 JPS63992 B2 JP S63992B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- ray tube
- cathode ray
- circuit
- deflection yoke
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/641—Multi-purpose receivers, e.g. for auxiliary information
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Details Of Television Scanning (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は文字多重信号あるいはマイクロコンピ
ユータからのカラー信号をも映出することができ
るカラーテレビジヨン受像機の速度変調制御装置
に関するものである。DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a speed modulation control device for a color television receiver capable of displaying a character multiplex signal or a color signal from a microcomputer.
従来例の構成とその問題点
第１図は従来例における速度制御装置のブロツ
ク図である。チユーナ１、IF回路２を通つて来
たビデオ信号はビデオ処理回路３に加えられ、ス
イツチ４，５の可動端子ａが固定端子ｂに接続さ
れていると、ビデオ信号は出力回路６を通つて陰
極線管７に加えられる。ビデオ処理回路３の出力
の一部は速度変調回路（以下VM回路という）８
に加えられ、その出力が陰極線管７の偏向ヨーク
９に加えられて、画像の輪郭を補正するように構
成されている。スイツチ４，５の可動端子ａと固
定端子ｃに接続するとビデオ信号中に含まれてい
る文字多重信号が文字多重処理回路で処理され、
文字が陰極線管７に映出される。また、マイクロ
コンピユータ等から来たカラー信号はRGB入力
回路１１を出てスイツチ１２を通つて陰極線管７
に加えられる。上記文字多重処理回路１０と
RGB入力回路１１はアダプターとして選択的に
カラーテレビジヨン受像機に付加される。Configuration of Conventional Example and Its Problems FIG. 1 is a block diagram of a speed control device in a conventional example. The video signal that has passed through the tuner 1 and the IF circuit 2 is applied to the video processing circuit 3, and when the movable terminals a of the switches 4 and 5 are connected to the fixed terminal b, the video signal is passed through the output circuit 6. added to the cathode ray tube 7. A part of the output of the video processing circuit 3 is supplied to a velocity modulation circuit (hereinafter referred to as VM circuit) 8
and its output is applied to the deflection yoke 9 of the cathode ray tube 7 to correct the contour of the image. When connected to the movable terminals a and fixed terminals c of switches 4 and 5, the character multiplex signal contained in the video signal is processed by the character multiplex processing circuit.
Characters are projected onto the cathode ray tube 7. Also, the color signal coming from the microcomputer etc. exits the RGB input circuit 11 and passes through the switch 12 to the cathode ray tube 7.
added to. The above character multiprocessing circuit 10 and
The RGB input circuit 11 is optionally added to a color television receiver as an adapter.
この従来の装置は、テレビ信号を陰極線管７に
映出しないとき、すなわち、文字多重処理回路１
０あるいはRGB入力回路１１の出力が陰極線管
７に映出されている場合でもVM回路８は動作し
ており、ここにはテレビ信号が加わつている。従
つて、陰極線管７の画面とは全く関係のない速度
変調がかかつてしまい、画像がかえつて悪くなる
欠点がある。 This conventional device is used when the television signal is not projected on the cathode ray tube 7, that is, when the character multiplexing circuit 1
0 or the output of the RGB input circuit 11 is projected onto the cathode ray tube 7, the VM circuit 8 is in operation, and a television signal is added thereto. Therefore, speed modulation that is completely unrelated to the screen of the cathode ray tube 7 occurs, which has the disadvantage that the image becomes worse.
発明の目的
そこで、本発明は上記欠点を除去し、テレビ信
号を陰極線管に映出しないときに画像が悪くなら
ないなようにすることを目的とするものである。OBJECT OF THE INVENTION It is therefore an object of the present invention to eliminate the above-mentioned drawbacks and to prevent the image from deteriorating when a television signal is not projected onto a cathode ray tube.
発明の構成
本発明の特徴とするところはテレビ信号を陰極
線管に映出するか、上記ビデオ信号中に含まれる
文字多重信号あるいはマイクロコンピユータ等か
ら来るカラー信号を陰極線管に映出するかを切替
える切替回路を設け、この切替回路より前段部分
に存在するビデオ信号を速度変調回路に加え、そ
の出力を陰極線管の偏向ヨークに加えて、画像の
輪郭部分を補正するよう構成し、上記テレビ信号
映出時か上記文字多重信号あるいは上記カラー信
号映出時かを検出し、検出信号によつてスイツチ
ング回路を動作させて、上記テレビ信号映出時に
は上記偏向ヨークに速度変調がかかり、上記文字
多重あるいはカラー信号映出時には上記偏向ヨー
クに速度変調がかからないようにしたことにあ
る。Structure of the Invention The present invention is characterized by switching between displaying a television signal on a cathode ray tube, or displaying a character multiplex signal included in the video signal or a color signal coming from a microcomputer, etc. on a cathode ray tube. A switching circuit is provided, a video signal existing in the stage preceding the switching circuit is applied to a speed modulation circuit, and its output is applied to the deflection yoke of the cathode ray tube to correct the outline of the image, and the above-mentioned television signal image is A switching circuit is operated based on the detection signal, and when the TV signal is displayed, speed modulation is applied to the deflection yoke to display the character multiplex or color signal. The purpose is to prevent velocity modulation from being applied to the deflection yoke during color signal projection.
実施例の説明
以下本発明の実施例について図面を参照して説
明する。第２図はその一実施例を示しており、第
１図と同一部分は同一番号を付して詳細な説明を
省略する。この実施例の特徴とするところはスイ
ツチ４，５，１２がどの状態にあるかを検出し、
その状態でスイツチング回路１３を制御するよう
にしたことにある。このために電池１５をスイツ
チ１４の可動端子に接続し、H1、H2端子をスイ
ツチング回路１３に接続している。スイツチ４，
５，１２，１４は連動させておく。スイツチ４，
５がｃ端子のときスイツチ１４はH1端子に、ス
イツチ４，５がｂ端子のときスイツチ１４はＬ端
子になるようになつている。スイツチ１２がｃの
ときスイツチ１４はH2に、スイツチ１２がｂの
ときスイツチ１４はＬ端子になるようになつてい
る。つまり、テレビ信号が映出されるときはスイ
ツチング回路１３の電圧は、ローレベル、他のと
きはハイレベルになる。このスイツチング回路１
３はたとえば第３図に示す回路が用いられ、入力
端子１６がハイレベルのとき、出力端子１７もハ
イレベル、入力端子１６がローレベルのとき出力
端子１７もローレベルになる。このハイ、ローの
信号でVM回路８を制御する。つまりハイのとき
VM回路８の動作を停止して偏向ヨーク９に速度
変調信号が加わらないようにする。DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 2 shows one embodiment of the present invention, and the same parts as in FIG. 1 are given the same numbers and detailed explanations are omitted. The feature of this embodiment is that it detects which state the switches 4, 5, and 12 are in;
The switching circuit 13 is controlled in this state. For this purpose, the battery 15 is connected to the movable terminal of the switch 14, and the H 1 and H 2 terminals are connected to the switching circuit 13. switch 4,
5, 12, and 14 are linked. switch 4,
When switch 5 is the c terminal, the switch 14 becomes the H1 terminal, and when switches 4 and 5 are the b terminal, the switch 14 becomes the L terminal. When the switch 12 is set to c, the switch 14 is set to H2 , and when the switch 12 is set to b, the switch 14 is set to the L terminal. That is, the voltage of the switching circuit 13 is at a low level when a television signal is displayed, and at a high level at other times. This switching circuit 1
3 is a circuit shown in FIG. 3, for example, when the input terminal 16 is at a high level, the output terminal 17 is also at a high level, and when the input terminal 16 is at a low level, the output terminal 17 is also at a low level. The VM circuit 8 is controlled by these high and low signals. In other words, when it's high
The operation of the VM circuit 8 is stopped to prevent the velocity modulation signal from being applied to the deflection yoke 9.
発明の効果
以上のように本発明によれば、文字多重信号や
外来のRGB信号を陰極線管に映出する場合には
速度変調信号が偏向ヨークに加わらないので画像
が悪くなることがないものである。Effects of the Invention As described above, according to the present invention, when projecting a character multiplex signal or an external RGB signal onto a cathode ray tube, the speed modulation signal is not applied to the deflection yoke, so the image does not deteriorate. be.
第１図は従来例における速度変調制御装置のブ
ロツク線図、第２図は本発明の一実施例における
速度変調制御装置のブロツク線図、第３図は同装
置の一部分の回路図である。
３……ビデオ処理回路、４，５，１２，１４…
…スイツチ、１０……文字多重処理回路、１１…
…RGB入力回路、１５……電池、１３……スイ
ツチング回路、８……VM回路、７……陰極線
管、９……偏向ヨーク。
FIG. 1 is a block diagram of a speed modulation control device in a conventional example, FIG. 2 is a block diagram of a speed modulation control device in an embodiment of the present invention, and FIG. 3 is a circuit diagram of a portion of the same device. 3...Video processing circuit, 4, 5, 12, 14...
...Switch, 10...Character multiple processing circuit, 11...
...RGB input circuit, 15 ... battery, 13 ... switching circuit, 8 ... VM circuit, 7 ... cathode ray tube, 9 ... deflection yoke.
Claims (1)
デオ信号中に含まれる文字多重信号あるいはマイ
クロコンピユータ等から来るカラー信号を陰極線
管に映出するかを切替える切替回路を設け、この
切替回路より前段部分に存在するビデオ信号を速
度変調回路に加え、その出力を陰極線管の偏向ヨ
ークに加えて画像の輪郭を補正するよう構成し、
上記テレビ信号映出時か上記文字多重信号あるい
は上記カラー信号映出時かを検出し、検出信号に
よつてスイツチング回路を動作させて、上記テレ
ビ信号映出時には上記偏向ヨークに速度変調がか
かり、上記文字多重信号あるいはカラー信号映出
時には上記偏向ヨークに速度変調がかからないよ
うにしたことを特徴とする速度変調制御装置。1. A switching circuit is provided to switch between displaying a television signal on a cathode ray tube, or displaying a character multiplex signal included in the video signal or a color signal coming from a microcomputer, etc. on a cathode ray tube. the video signal present in the section is applied to a velocity modulation circuit, the output of which is applied to a deflection yoke of the cathode ray tube to correct image contour;
Detecting whether the television signal, the character multiplex signal, or the color signal is being displayed, operating a switching circuit based on the detection signal, and applying velocity modulation to the deflection yoke when the television signal is being displayed; A speed modulation control device characterized in that speed modulation is not applied to the deflection yoke during projection of the character multiplexed signal or color signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57105961A JPS58222671A (en) | 1982-06-18 | 1982-06-18 | Speed modulation control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57105961A JPS58222671A (en) | 1982-06-18 | 1982-06-18 | Speed modulation control device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58222671A JPS58222671A (en) | 1983-12-24 |
| JPS63992B2 true JPS63992B2 (en) | 1988-01-09 |
Family
ID=14421393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57105961A Granted JPS58222671A (en) | 1982-06-18 | 1982-06-18 | Speed modulation control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58222671A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0669213B2 (en) * | 1984-03-30 | 1994-08-31 | シャープ株式会社 | Video image contour correction device |
| JPS61167280A (en) * | 1985-01-19 | 1986-07-28 | Sony Corp | Control circuit for velocity-modulating circuit in a television receiver |
| JPH0746830B2 (en) * | 1985-08-28 | 1995-05-17 | 株式会社日立製作所 | Vertical contour correction circuit for TV receiver |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5516458U (en) * | 1978-07-19 | 1980-02-01 | ||
| JPS5915594B2 (en) * | 1978-10-18 | 1984-04-10 | 松下電器産業株式会社 | color television receiver |
-
1982
- 1982-06-18 JP JP57105961A patent/JPS58222671A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58222671A (en) | 1983-12-24 |
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