JPS6398647U - - Google Patents
Info
- Publication number
- JPS6398647U JPS6398647U JP19476086U JP19476086U JPS6398647U JP S6398647 U JPS6398647 U JP S6398647U JP 19476086 U JP19476086 U JP 19476086U JP 19476086 U JP19476086 U JP 19476086U JP S6398647 U JPS6398647 U JP S6398647U
- Authority
- JP
- Japan
- Prior art keywords
- metal substrates
- insulating film
- conductive path
- circuit elements
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002184 metal Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Combinations Of Printed Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Casings For Electric Apparatus (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19476086U JPH0442937Y2 (de) | 1986-12-18 | 1986-12-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19476086U JPH0442937Y2 (de) | 1986-12-18 | 1986-12-18 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6398647U true JPS6398647U (de) | 1988-06-25 |
| JPH0442937Y2 JPH0442937Y2 (de) | 1992-10-12 |
Family
ID=31152030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19476086U Expired JPH0442937Y2 (de) | 1986-12-18 | 1986-12-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0442937Y2 (de) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012151173A (ja) * | 2011-01-17 | 2012-08-09 | Nec Corp | ３次元実装型半導体装置、および電子機器 |
| JP2016219715A (ja) * | 2015-05-26 | 2016-12-22 | 住友ベークライト株式会社 | 絶縁ゲートバイポーラトランジスタ素子、樹脂組成物およびサージ対策部材 |
-
1986
- 1986-12-18 JP JP19476086U patent/JPH0442937Y2/ja not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012151173A (ja) * | 2011-01-17 | 2012-08-09 | Nec Corp | ３次元実装型半導体装置、および電子機器 |
| JP2016219715A (ja) * | 2015-05-26 | 2016-12-22 | 住友ベークライト株式会社 | 絶縁ゲートバイポーラトランジスタ素子、樹脂組成物およびサージ対策部材 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0442937Y2 (de) | 1992-10-12 |