JPS6398189A - Manufacture of ic chip mounting multilayer board - Google Patents

Manufacture of ic chip mounting multilayer board

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Publication number
JPS6398189A
JPS6398189A JP61243228A JP24322886A JPS6398189A JP S6398189 A JPS6398189 A JP S6398189A JP 61243228 A JP61243228 A JP 61243228A JP 24322886 A JP24322886 A JP 24322886A JP S6398189 A JPS6398189 A JP S6398189A
Authority
JP
Japan
Prior art keywords
chip
multilayer
mounting
multilayer board
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61243228A
Other languages
Japanese (ja)
Inventor
池口 信之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Gas Chemical Co Inc
Original Assignee
Mitsubishi Gas Chemical Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Gas Chemical Co Inc filed Critical Mitsubishi Gas Chemical Co Inc
Priority to JP61243228A priority Critical patent/JPS6398189A/en
Publication of JPS6398189A publication Critical patent/JPS6398189A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ICチップ搭載用多層板の製造法であり、多
層化用の低流動性接着シートからの樹脂流れによる内層
用プリント配線板に形成された端子接続部の汚れからの
保護を信頼性よく達成したものであり、特に好ましい態
様においては、耐マイグレーション性(高湿度下、配線
導体間の絶縁が導体金属イオンの拡散により破壊される
現象)が生じ難く、また耐水蒸気性の優れた多層板を提
供するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is a method for manufacturing a multilayer board for mounting an IC chip, and is a method for manufacturing a multilayer board for mounting an IC chip. It reliably protects the formed terminal connections from contamination, and in a particularly preferred embodiment, has migration resistance (under high humidity, the insulation between wiring conductors is destroyed by the diffusion of conductor metal ions). The purpose of the present invention is to provide a multilayer board that is less likely to cause this phenomenon and has excellent water vapor resistance.

〔従来の技術およびその問題点〕[Conventional technology and its problems]

ICチップ搭載用の多層板、例えば、多層ピン・グリッ
ド・アレイ(多層PGA)の基板としてはセラミックス
が使用されている。しかし、セラミックスは耐衝撃性に
劣り、誘電率が高く、加工性に劣るなどの問題がある。
Ceramics are used as multilayer boards for mounting IC chips, such as multilayer pin grid array (multilayer PGA) substrates. However, ceramics have problems such as poor impact resistance, high dielectric constant, and poor workability.

しかも、急速に高密度化しているICチップを搭載する
必要性から、現在はより低誘電率で、加工が簡便でより
低価格のものが要求されている。
Moreover, because of the need to mount IC chips, which are rapidly increasing in density, there is now a demand for lower dielectric constants, easier processing, and lower costs.

又、プラスチック製の両面板を使用してプラスチック両
面PGA基板が製造されているが、加工性の点から、ピ
ン数を150以上とした場合には、線巾及び線間間隔を
より狭くすることが必須となる為、不良が発生し易いと
いう問題点があった。
Also, plastic double-sided PGA boards are manufactured using plastic double-sided boards, but from the viewpoint of processability, when the number of pins is set to 150 or more, the line width and the line spacing must be narrower. Since this is essential, there is a problem in that defects are likely to occur.

この不良の発生の低減策として、多層化する方法がある
が、公知の低流動性の多層化用接着シートは、耐マイグ
レーション性に劣り、耐水蒸気性も不十分であるという
実用上の問題がある。さらに、この接着シートの樹脂流
れを100ρ以下にすると、プリント配線金属箔(通常
は銅箔)の間に樹脂が充分に充填されず、層間密着不良
が生じるという問題が生じ、逆に、樹脂流れを必要充分
に設定した場合には端子部先端まで樹脂が流れて端子部
を汚染し、ワイヤボンディング不良が発生するという問
題点が生じるものである。この解決策として従来は、プ
リント配線銅箔間隙に樹脂を予め充填したプリント配線
板を使用する方法がとられていたが、工程面で不利とな
る。
One way to reduce the occurrence of defects is to use multiple layers, but known low-flow multilayer adhesive sheets have practical problems such as poor migration resistance and insufficient water vapor resistance. be. Furthermore, if the resin flow of this adhesive sheet is less than 100ρ, the resin will not be sufficiently filled between the printed wiring metal foils (usually copper foils), resulting in poor interlayer adhesion. If this is set to a necessary and sufficient level, the problem arises that the resin flows to the tip of the terminal and contaminates the terminal, resulting in defective wire bonding. A conventional solution to this problem has been to use a printed wiring board in which the gaps between the printed wiring copper foils are filled with resin in advance, but this is disadvantageous in terms of the process.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、上記の問題点を解決する方法について鋭意検
討した結果、多層化積層成形に先立って多層化用プリン
ト配線板の端子の接続部の周縁に、多層化接着用シート
からの樹脂流れにより該端子接続部が汚染されることを
防止する被T!ii層を形成する方法を見出し、これに
基づいて完成したものである。
As a result of extensive research into methods for solving the above problems, the present invention has developed a method for applying resin flow from a multilayer adhesive sheet to the periphery of the terminal connection part of a multilayer printed wiring board prior to multilayer lamination molding. To prevent the terminal connection from being contaminated! A method for forming layer ii was discovered and completed based on this method.

すなわち、本発明は、少なくともICチップ搭載用の穴
及び接続用の端子部を有する多層板の製造法において、
内層を形成するプリント配線板として、ICチップ接続
用の端子の接続部を残してその周縁を光若しくは熱硬化
型のレジストを用いて被覆した多層化用のプリント配線
板を使用し、これを所定位置に所定の大きさの孔を形成
した低流動性接着シートを用いて多層化積層成形するこ
とを特徴とするICチップ搭載用多層板の製造法であり
、好ましい実施態様においては、該低流動性接着シート
が、(a)多官能性シアン酸エステル樹脂組成物、(b
)実質的に非結晶性の熱可塑性飽和ポリエステル樹脂及
び(c)硬化触媒を必須成分とする熱硬化性樹脂組成物
のシート若しくはフィルム又は該熱硬化性樹脂組成物を
補強基材に含浸・乾燥してEl−stage化してなる
ものを用いること、更に多層化積層成形を100mmH
g以下の減圧状態で行うことを特徴とするものである。
That is, the present invention provides a method for manufacturing a multilayer board having at least a hole for mounting an IC chip and a terminal portion for connection.
As the printed wiring board forming the inner layer, a multilayer printed wiring board is used in which the periphery is coated with a photo- or thermosetting resist, leaving the terminal connection part for connecting the IC chip, and this is coated in a specified manner. A method for producing a multilayer board for mounting an IC chip, which is characterized by performing multilayer lamination molding using a low-flow adhesive sheet in which holes of a predetermined size are formed at positions, and in a preferred embodiment, the low-flow adhesive sheet The adhesive sheet includes (a) a polyfunctional cyanate ester resin composition, (b)
) A sheet or film of a thermosetting resin composition containing a substantially amorphous thermoplastic saturated polyester resin and (c) a curing catalyst as essential components, or a reinforcing base material is impregnated with the thermosetting resin composition and dried. 100mmH of multilayer lamination molding.
This method is characterized in that it is carried out under a reduced pressure of less than 100 g.

以下、本発明の構成について説明する。The configuration of the present invention will be explained below.

本発明のICチップ搭載用の多層板(以下、単に「本多
層板」という)とは、ICチップの搭載用の穴部とその
穴周囲に搭載したICチップとの接続用の通常金メッキ
された、通常、巾0.1〜2mm、間隔0.1〜1 m
m、長さ1〜5mmのICチップとの接続用の端子を多
数形成してなる端子部を設けた中間層を少なくとも1層
有する多層板であり、スルーホールメッキによる層間の
配線、多数のピンを立てた所謂「ピン・グリッド・アレ
イ」などを含むものである。
The multilayer board for mounting an IC chip of the present invention (hereinafter simply referred to as "this multilayer board") is a hole for mounting an IC chip and a hole for connecting the IC chip mounted around the hole, which is usually gold-plated. , usually width 0.1-2mm, interval 0.1-1m
It is a multilayer board that has at least one intermediate layer with a terminal section formed by forming a large number of terminals for connection with an IC chip with a length of 1 to 5 mm, and has interlayer wiring by through-hole plating and a large number of pins. This includes the so-called ``pin grid array,'' which is a ``pin grid array.''

本多層板の製造工程は、通常の多層化積層成形方法が使
用され、例えば、両面銅張積層板の片面に公知方法で端
子部を含む配線網又はICチップ搭載部若しくはICチ
ップ搭載部に穴を掘り込んでなり、他面に所望の配線網
を形成してなるプリント配線板(基板I)、所望の孔及
び端子部を含む配線網を形成した片面銅張積層板(片面
板■)及び所望の孔を形成した接着シー)Iを準備し、
基板Iに片面板■を接着シートIを介して位置合わせし
て所望の組数重ね一回の積層成形により多層板とする方
法;両面銅張積層板の片面に公知方法で端子部を含む配
線網又はICチップ搭載部若しくはICチップ搭載部に
穴を掘り込んでなり、他面未処理の基板■と片面銅張積
層板とを必要に応じて所定の孔を形成した接着シー)I
で多層化積層成形し、積層した銅箔面に予め設けた基準
マークに基づいて端子部を含む配線網を形成し、再びこ
の上に片面銅張積層板を積層成形し、配線網の作製をす
る工程を繰り返した後、必要に応じてスルーホールメッ
キ、両面の配線網の形成を行い、切削加工してIC装着
部及び端子部を露出させる方法、その他何れの方法でも
よい。
In the manufacturing process of this multilayer board, a normal multilayer lamination molding method is used. For example, a wiring network including a terminal part, an IC chip mounting part, or an IC chip mounting part is drilled on one side of a double-sided copper-clad laminate using a known method. A printed wiring board (substrate I) formed by digging a hole and forming a desired wiring network on the other side, a single-sided copper-clad laminate (single-sided board ■) formed with a wiring network including desired holes and terminals, and Prepare adhesive sheet (I) with desired holes formed,
A method of forming a multilayer board by aligning a single-sided board (■) to a substrate I via an adhesive sheet I and laminating a desired number of sets in one go; wiring including a terminal portion on one side of a double-sided copper-clad laminate using a known method. An adhesive sheet made by digging holes in the net or the IC chip mounting part or the IC chip mounting part, and forming predetermined holes as necessary between the untreated substrate on the other side and the copper-clad laminate on one side.
A wiring network including terminals is formed based on reference marks pre-set on the laminated copper foil surface, and a single-sided copper-clad laminate is laminated on top of this again to create a wiring network. After repeating these steps, if necessary, through-hole plating is performed, wiring networks are formed on both sides, and cutting is performed to expose the IC mounting portion and terminal portion, or any other method may be used.

本多層板に使用するプリント配線板用の積層板としては
、ガラス繊維、石英繊維、全芳昏族ポリアミド、ポリイ
ミド、セミカーボン繊維などの単独もしくは混合使用し
てなる不織布や織布強化の従来の両面又は片面金属?δ
張積層板であれば何れも使用可能であるが、具体的には
ガラス布エポキシ積層板、耐熱性ガラス布エポキシ積層
板、石英繊維布エポキシ積層板、ガラス布シアン酸エス
テル系樹脂積層板(三菱瓦斯化学G1.)製、CCL−
II 800゜(:CL−II 830.CCL−II
 870他)、石英繊維布シアン酸エステル系樹脂積層
板、ガラス布ポリイミド系積層板などの熱硬化樹脂系の
積層板および高耐熱性の熱可塑性樹脂系の積層板が例示
される。
The laminates for printed wiring boards used in this multilayer board include conventional nonwoven fabrics or woven fabrics reinforced with glass fibers, quartz fibers, wholly aromatic polyamides, polyimides, semicarbon fibers, etc., used alone or in combination. Double-sided or single-sided metal? δ
Any stretched laminate can be used, but specifically, glass cloth epoxy laminates, heat-resistant glass cloth epoxy laminates, quartz fiber cloth epoxy laminates, glass cloth cyanate ester resin laminates (Mitsubishi Manufactured by Gas Kagaku G1.), CCL-
II 800゜(:CL-II 830.CCL-II
870, etc.), thermosetting resin-based laminates such as quartz fiber cloth cyanate ester-based resin laminates, glass cloth polyimide-based laminates, and highly heat-resistant thermoplastic resin-based laminates.

端子部及び配線部を形成した基板11積層した片面板■
又は片面板■の接続端子部の周縁に細い枠を形成するた
めに用いる光若しくは熱硬化性のレジストとしては、通
常プリント配線板の製造に使用されている光若しくは熱
硬化性のレジストが使用できるものであり、通常のスク
リーン法やフォトレジスト法、特に端子間隔が狭い場合
にはフォトレジストによる方法が好適である。この端子
接続部周縁に形成する被覆層は、個々の端子接続部を端
子部の内り;1:から通常1〜5 mm程度残して、そ
の端子間及びその外周周囲部を被覆する方法によって形
成する。
Board 11 laminated single-sided board with terminals and wiring formed
Alternatively, as the photo- or thermosetting resist used to form a thin frame around the connection terminal part of the single-sided board (■), a photo- or thermosetting resist that is normally used in the manufacture of printed wiring boards can be used. Therefore, the usual screen method or photoresist method, and especially when the terminal spacing is narrow, the method using photoresist is suitable. The coating layer formed around the periphery of the terminal connection part is formed by a method of covering the space between the terminals and the outer periphery of each terminal connection part, usually leaving about 1 to 5 mm from the inner part of the terminal part. do.

本発明の多口化接着用の低流動性接着シートとしては、
通常の多層化用接着シートの場合には樹脂流れが0.0
5〜3 mmの範囲のものであれば使用可能である。樹
脂流れが少なすぎると基板との密着性が悪く、銅9Iゴ
で形成した配線導体間への樹脂の充填が不十分となり、
逆に樹脂流れが大きすぎると樹脂が前記で説明した樹脂
枠を超えて端子部を汚染することとなる。このような特
性の他に、密着性、接着性、その他の物性面から本発明
においては、(a)多官能性シアン酸エステル樹脂組成
物、(b)実質的に非結晶性の熱可塑性飽和ポリエステ
ル樹脂及び(c)硬化触媒を必須成分とする熱硬化性樹
脂組成物のシートもしくはフィルム又は核熱硬化製樹脂
組成物を補強基材に含浸・乾燥してB−8tage化し
てなるもの(特開昭60−192779 、同60−2
33175に記載)が好ましい。ここに、樹脂成分(a
)である多官能性シアン酸エステル樹脂組成物とは、シ
アナト基を有する多官能性シアン酸エステル、そのプレ
ポリマー等を必須成分としてなるものであり、シアナト
樹脂(特公昭41−1928 、同45−11712、
同44−1222 、DIE−1,190,184等)
、シアン酸エステル−マレイミド樹脂、シアン酸エステ
ル−マレイミド−エポキシ樹脂(特公昭54−3044
0、同52−31279、USP−4,110,364
等)、シアン酸エステル−エポキシ樹脂(特公昭46−
41112)などで代表されるものである。又、(b)
成分の実質的に非結晶性の熱可塑性飽和ポリエステル樹
脂とは、芳昏族乃至脂肪族のジカルボン酸と脂肪族乃至
脂環族のジオール若しくはそのプレポリマーとを主成分
として重縮合させてなるものである。本発明においては
、通常、末端官能基数より算出される数平均分子量が1
.500〜25.000、好ましくは5.000〜22
.000のものが相溶性などより好ましい。また、水酸
基価が1〜30mg−KOII / gのものが好適で
ある。
The low-fluidity adhesive sheet for multi-mouth adhesive of the present invention includes:
In the case of a normal multilayer adhesive sheet, the resin flow is 0.0
Anything in the range of 5 to 3 mm can be used. If the resin flow is too small, the adhesion with the board will be poor, and the resin will not be filled between the wiring conductors formed with copper 9I rubber.
On the other hand, if the resin flow is too large, the resin will exceed the resin frame described above and contaminate the terminal portion. In addition to these properties, from the viewpoint of adhesion, adhesion, and other physical properties, the present invention uses (a) a polyfunctional cyanate ester resin composition, (b) a substantially non-crystalline thermoplastic saturated B-8tage is obtained by impregnating a reinforcing base material with a sheet or film of a thermosetting resin composition containing a polyester resin and (c) a curing catalyst as essential components, or a nuclear thermosetting resin composition and drying it. Kaisho 60-192779, Kaisho 60-2
33175) is preferred. Here, the resin component (a
) is a polyfunctional cyanate ester resin composition that contains a polyfunctional cyanate ester having a cyanato group, its prepolymer, etc. as essential components, and is a cyanato resin (Japanese Patent Publication No. 41-1928, No. 45). -11712,
44-1222, DIE-1, 190, 184, etc.)
, cyanate ester-maleimide resin, cyanate ester-maleimide-epoxy resin (Japanese Patent Publication No. 54-3044
0, 52-31279, USP-4,110,364
etc.), cyanate ester-epoxy resin (Special Publication No. 46-
41112) and others. Also, (b)
The substantially non-crystalline thermoplastic saturated polyester resin as a component is one obtained by polycondensing an aromatic or aliphatic dicarboxylic acid with an aliphatic or alicyclic diol or its prepolymer as a main component. It is. In the present invention, the number average molecular weight calculated from the number of terminal functional groups is usually 1
.. 500-25,000, preferably 5,000-22
.. 000 is preferable due to compatibility. Moreover, those having a hydroxyl value of 1 to 30 mg-KOII/g are suitable.

これは、該ポリエステル樹脂に遊離の水酸基もしくはカ
ルボキシル基が過剰に有った場合には、これらの基と(
a)成分のシアナト基とが徐々に常温においても反応し
、組成物の保存安定性が劣ることとなるためである。ま
た、結晶性は低い程好ましく、用いる酸およびアルコー
ル成分の種類および使用量比を選択されるものである。
This means that if the polyester resin has an excess of free hydroxyl groups or carboxyl groups, these groups and (
This is because the cyanato group of component a) gradually reacts even at room temperature, resulting in poor storage stability of the composition. Further, the lower the crystallinity, the better, and the type and amount ratio of the acid and alcohol components to be used are selected.

かかる実質的に非結晶性の熱可塑性飽和ポリエステル樹
脂としては、日本合成化学工業0幼から商品名「ポリエ
スタ−」として市販されているものが好適である。
As such a substantially non-crystalline thermoplastic saturated polyester resin, one commercially available from Nippon Gosei Kagaku Kogyo Co., Ltd. under the trade name "Polyester" is suitable.

上記した成分(a)と成分(b)との配合比率は、特に
限定のないものであるが、通常、成分(a) 30〜9
5重量部、成分(b)70〜5重量部であり、成分(a
)及び(b)の混合方法は特に限定されないが、通常、
(a)成分の溶液を調製し、これに(b)IliW分又
は(b)成分の溶液を混合する方法; jl[溶剤でそ
れぞれの成分を溶融混合した後、溶液とする方法;更に
、前記した併用可能成分のなかの反応性希釈剤などを使
用し無溶剤の液状乃至ペースト状の組成物とする方法等
によって樹脂組成物を予め調製し、これに必要に応じて
公知の触媒、特に有機過酸化物、有機金属塩などを添加
し混合する方法;前記した混合時に触媒等を併用して混
合する方法などによる。有機溶媒としては好適には、メ
チルエチルケトン、アセトン、トルエン、キシレン、ト
リクロロエチレン、ジオキサンなどが例示され、濃度と
しては含浸に必要な樹脂量及び粘度により選択されるが
、通常、20〜60重量%が好適である。
The blending ratio of component (a) and component (b) described above is not particularly limited, but usually component (a) is 30 to 9
5 parts by weight, 70 to 5 parts by weight of component (b), and 70 to 5 parts by weight of component (a).
) and (b) are not particularly limited, but usually,
A method of preparing a solution of component (a) and mixing it with a solution of (b) IliW or component (b); A resin composition is prepared in advance by a method of making a solvent-free liquid or paste composition using a reactive diluent among the components that can be used in combination, and if necessary, a known catalyst, especially an organic A method of adding and mixing a peroxide, an organic metal salt, etc.; a method of using a catalyst or the like at the time of mixing as described above; and the like. Suitable examples of the organic solvent include methyl ethyl ketone, acetone, toluene, xylene, trichloroethylene, dioxane, etc., and the concentration is selected depending on the amount of resin and viscosity required for impregnation, but usually 20 to 60% by weight is preferable. It is.

更に、(c)成分の補強基材としては、前記した基板I
に使用するものと同様の繊維布基材類、及び四フッ化エ
チレン製の連続気泡の多孔質基材が例示され、通常、厚
み0.03〜0.2mm程度のものである。
Furthermore, as the reinforcing base material of component (c), the above-mentioned substrate I
Examples include fiber cloth substrates similar to those used in , and open-cell porous substrates made of tetrafluoroethylene, and usually have a thickness of about 0.03 to 0.2 mm.

上記で調製した本樹脂溶液を(c)成分の補強基材に樹
脂量35〜85重世%の範囲となるように含浸した後、
120〜170℃、1〜20分間乾爆して溶剤を除去し
、所謂r[3−3−stage J化する。
After impregnating the reinforcing base material of component (c) with the resin solution prepared above so that the resin amount is in the range of 35 to 85%,
The solvent is removed by dry blasting at 120 to 170° C. for 1 to 20 minutes, resulting in so-called r[3-3-stage J.

多層化積層成形の条件は、触媒・組成成分、基材の種類
などによっても変化するが、通常100〜300亡、0
.1〜100 kg / cnf、好ましくは5〜50
kgZCイ、特に10〜40kg / cnfの範囲内
である。又、本発明においては、多層化積層成形を10
0mmHg以下の減圧状態で実施することが、ボイドの
発生などを無くす面から特に好適である。
The conditions for multilayer lamination molding vary depending on the catalyst, composition components, type of base material, etc., but are usually 100 to 300% or 0%.
.. 1-100 kg/cnf, preferably 5-50
kgZC, especially within the range of 10-40 kg/cnf. In addition, in the present invention, multilayer lamination molding is carried out in 10
It is particularly preferable to carry out the process under reduced pressure of 0 mmHg or less in order to avoid the occurrence of voids.

以下、実施例、比較例によって本発明をさらに具体的に
説明する。尚、実施例、比較例中の部は特に断らない限
り重量部である。
Hereinafter, the present invention will be explained in more detail with reference to Examples and Comparative Examples. In addition, parts in Examples and Comparative Examples are parts by weight unless otherwise specified.

実施例−1 2,2−ビス(4−シアナトフェニル)プロパン750
部を160℃で4時間予備反応させてプレポリマーとし
た。このプレポリマーに実質的に非結晶性の熱可塑性飽
和ポリエステル樹脂(商品名:ポリニスクー LP−0
35、日本合成化学工業0菊製、末端官能基数より算出
される数平均分子ffi 16,000 、水酸基価6
mg KOII/ g ) 250部、さらにビスフェ
ノールA型エポキシ樹脂(商品名:エピコート828、
油化シェルエポキシ()菊製)50部を加え、メチルエ
チルケトン(以下、MCKという)に溶解混合し、濃度
60%の溶液とした(フェス(a)という)。
Example-1 2,2-bis(4-cyanatophenyl)propane 750
A prepolymer was obtained by preliminarily reacting a portion at 160° C. for 4 hours. This prepolymer is a substantially non-crystalline thermoplastic saturated polyester resin (trade name: POLYNISK LP-0).
35, manufactured by Nippon Gosei Chemical Industry 0 Kiku, number average molecule ffi calculated from the number of terminal functional groups: 16,000, hydroxyl value: 6
mg KOII/g) 250 parts, and bisphenol A epoxy resin (trade name: Epicote 828,
50 parts of Yuka Shell Epoxy (manufactured by Kiku) was added and dissolved and mixed in methyl ethyl ketone (hereinafter referred to as MCK) to form a solution with a concentration of 60% (referred to as FES (a)).

フェス(a)に触媒としてオクチル酸亜鉛0.12部を
加え均一に混合し、この溶液を厚み150虜の表面処理
した離型紙の片面に連続的に塗布して、接着剤層の厚み
4(Junの1313−stageの離型紙付き接着シ
ート(以下、シー1− Iという)を製造した。
Add 0.12 parts of zinc octylate as a catalyst to the adhesive layer (a) and mix uniformly. Apply this solution continuously to one side of surface-treated release paper with a thickness of 150 mm to form an adhesive layer with a thickness of 4 mm. An adhesive sheet with a release paper (hereinafter referred to as "Sheet 1-I") of Jun's 1313-stage was manufactured.

他方、熱硬化性のポリイミド樹脂(商品名;KIERI
MID 601、ロース・ブーラン社製)700部とエ
ポキシ樹脂(商品名;エピコート1001、油化シェル
エポキシ01)製)300部とをN−メチルピロリドン
に溶解し、触媒として過酸化ベンゾイル1部を添加した
ものを厚み0.1mmのガラス織布に含浸・乾燥してI
Ill−stageのプリプレグとし、このプリプレグ
と厚み35ρの電解銅箔を用いて、180℃、20kg
/cITIで1時間、更に温度を230℃に昇温後、4
0kg/crdで15分間積層成形して、厚み0.3m
mの片面銅張積層板及び厚み0.7mmの両面銅張積層
板を製造した。
On the other hand, thermosetting polyimide resin (product name: KIERI
700 parts of MID 601 (manufactured by Roth-Boulin) and 300 parts of an epoxy resin (product name: Epicote 1001, Yuka Shell Epoxy 01) were dissolved in N-methylpyrrolidone, and 1 part of benzoyl peroxide was added as a catalyst. The material was impregnated into a 0.1 mm thick glass woven cloth and dried.
Ill-stage prepreg was used, and using this prepreg and electrolytic copper foil with a thickness of 35ρ, 20 kg was heated at 180°C.
/cITI for 1 hour, and after further increasing the temperature to 230°C,
Laminated for 15 minutes at 0kg/crd to a thickness of 0.3m.
A single-sided copper-clad laminate with a thickness of 0.7 mm and a double-sided copper-clad laminate with a thickness of 0.7 mm were manufactured.

この両面銅張積層板に、公知方法により、端子接続部の
11及び間隔0.5胴、長さ1.0mmの金メッキした
端子部を形成し、ICチップ装青部を彫り込みし、裏面
にも所望の配線網並びにその保護膜を形成して基板■と
し、片面銅張積層板も同様に端子部には金メッキを施し
その周囲の配線網には保護膜を形成した片面板■を作製
した。基板Iの端子部はその端子接続部間及びその周囲
外周に端子内端から1.1m+nの残して巾0.5mm
の被覆層を多官能性シアン酸エステル系レジスト(商品
名:01M450、三菱瓦斯化学0幼製)でスクリーン
法にて印刷し、150℃で40分間加熱硬化させた。
On this double-sided copper-clad laminate, a gold-plated terminal part 11 with a terminal connection part 11, a pitch of 0.5 mm, and a length of 1.0 mm was formed by a known method, and a blue IC chip mounting part was engraved. A desired wiring network and its protective film were formed to form a substrate (2), and a single-sided copper-clad laminate was similarly plated with gold at the terminals and a protective film was formed on the surrounding wiring network to produce a single-sided board (2). The terminal part of the board I has a width of 0.5 mm between the terminal connecting parts and the outer periphery of the terminal, leaving 1.1 m + n from the inner end of the terminal.
The coating layer was printed with a polyfunctional cyanate ester resist (trade name: 01M450, manufactured by Mitsubishi Gas Chemical Co., Ltd.) by a screen method, and was heated and cured at 150° C. for 40 minutes.

次に、上記で得たシートIを前記で得た片面板■の裏面
に重ね、温度120℃の熱ロールで接着剤層を片面板H
に転写した後、ICチップ装着部を所定の大きさに打抜
きした。
Next, the sheet I obtained above was stacked on the back side of the single-sided plate H obtained above, and the adhesive layer was applied to the single-sided plate H using a hot roll at a temperature of 120°C.
After the image was transferred to , the IC chip mounting portion was punched out to a predetermined size.

基板工の端子部形成面側に、接着シート層付きの片面板
■を位置合わせして重ね、温度175℃、圧力20kg
 / cntで2時間積層成形し多層板を得た。
Align and stack the single-sided board with an adhesive sheet layer on the terminal forming side of the circuit board, and apply a temperature of 175℃ and a pressure of 20kg.
/ cnt for 2 hours to obtain a multilayer board.

この多層板の所定のピン立て位置に孔を開け、ついで外
形加工し、スルーホールメッキを施すことなくピン立て
を行い3層のプラスチックPGAとした。孔開は時にス
ミアの発生を観察したが、スミア発生は認められなかっ
た。
Holes were drilled at predetermined pin positions in this multilayer board, the external shape was processed, and pin positions were formed without through-hole plating, resulting in a three-layer plastic PGA. Occasionally, smear formation was observed during hole opening, but no smear formation was observed.

このプラスチックPGAの内層の表面抵抗劣化を130
℃、2.8気圧のプレッシャークツカーテストで測定し
た結果、抵抗値が108Ω以下になるまでの時間は38
0時間であった。
The surface resistance deterioration of the inner layer of this plastic PGA is 130
As a result of measuring with a pressure tester at ℃ and 2.8 atm, the time it takes for the resistance value to decrease to 108 Ω or less is 38 Ω.
It was 0 hours.

また、接着シーI・の端子金メッキ部へのレジスト被覆
層を超えてのはみ出しは、85μm以下に止まるもので
あり、又、端子間被覆層上の流れは被覆層外端から0.
6mmであった(レジスト被覆層の無い場合は、2mm
程度である)。又、内層配線網間間隙について、断面切
断サンプルを顕微鏡観察した結果、空隙は全く認めらず
、更に、260℃の半田浴に20秒フロートによっても
層間剥離や膨れなどの不良の発生はなかった。
In addition, the protrusion of the adhesive sheet I beyond the resist coating layer to the terminal gold-plated portion is limited to 85 μm or less, and the flow on the inter-terminal coating layer is 0.5 μm from the outer edge of the coating layer.
6 mm (2 mm if there is no resist coating layer)
). Regarding the gaps between the inner layer wiring networks, microscopic observation of cross-sectional samples revealed no gaps at all, and no defects such as delamination or blistering occurred even after floating in a 260°C solder bath for 20 seconds. .

〔発明の作用および効果〕[Operation and effects of the invention]

以上の発明の詳細な説明および実施例等から明らかなよ
うに、本発明のICチップ搭載用多層板の製法によれば
、層間接着用のシートとして配線網の導体間間隙を充分
に充填できる樹脂流れの比較的大きい接着シートを使用
しても、樹脂流れによる端子部などの汚染が防止される
ものであり、多層化積属成形時に生じる問題を解決でき
るものであり、新規な工業的製法として実用性の極めて
大きいものである。
As is clear from the above detailed description of the invention and examples, the method for manufacturing a multilayer board for mounting an IC chip of the present invention uses a resin that can be used as a sheet for interlayer adhesion to sufficiently fill the gaps between conductors in a wiring network. Even if an adhesive sheet with a relatively large flow is used, contamination of terminal parts etc. due to resin flow can be prevented, and it can solve the problems that occur during multi-layer stack molding, and can be used as a new industrial manufacturing method. It is extremely practical.

更に、本発明の好ましい態様において使用する接着シー
トは銅のマイグレーション防止の効果が著しいものであ
り、実使用時の長期の信頼性にも優れたものとなるもの
である。
Further, the adhesive sheet used in a preferred embodiment of the present invention has a remarkable effect of preventing copper migration and has excellent long-term reliability during actual use.

Claims (1)

【特許請求の範囲】 1 少なくともICチップ搭載用の穴及び接続用の端子
部を有する多層板の製造法において、内層を形成するプ
リント配線板として、ICチップ接続用の端子の接続部
を残してその周縁を光若しくは熱硬化型のレジストを用
いて被覆した多層化用のプリント配線板を使用し、これ
を所定位置に所定の大きさの孔を形成した低流動性接着
シートを用いて多層化積層成形することを特徴とするI
Cチップ搭載用多層板の製造法。 2 該低流動性接着シートが、(a)多官能性シアン酸
エステル樹脂組成物、(b)実質的に非結晶性の熱可塑
性飽和ポリエステル樹脂及び(c)硬化触媒を必須成分
とする熱硬化性樹脂組成物のシート若しくはフィルム又
は該熱硬化性樹脂組成物を補強基材に含浸・乾燥してB
−stage化してなるものである特許請求の範囲第1
項記載のICチップ搭載用多層板の製造法。 3 多層化積層成形を100mmHg以下の減圧状態で
行う特許請求の範囲第1項または2項記載のICチップ
搭載用多層板の製造法。
[Claims] 1. In a method for manufacturing a multilayer board having at least holes for mounting an IC chip and terminal portions for connection, the printed wiring board forming an inner layer may leave a connection portion for a terminal for connecting an IC chip. A multilayer printed wiring board whose periphery is coated with photo- or thermosetting resist is used, and this is multilayered using a low-flow adhesive sheet with holes of a predetermined size formed at predetermined positions. I characterized by laminated molding
A method for manufacturing a multilayer board for mounting a C chip. 2. The low-fluidity adhesive sheet is a thermosetting adhesive sheet containing (a) a polyfunctional cyanate ester resin composition, (b) a substantially non-crystalline thermoplastic saturated polyester resin, and (c) a curing catalyst as essential components. A sheet or film of the thermosetting resin composition or the thermosetting resin composition is impregnated into a reinforcing base material and dried.
-Claim 1, which is obtained by converting it into a stage.
A method for manufacturing a multilayer board for mounting an IC chip as described in . 3. A method for manufacturing a multilayer board for mounting an IC chip according to claim 1 or 2, wherein the multilayer lamination molding is carried out under a reduced pressure of 100 mmHg or less.
JP61243228A 1986-10-15 1986-10-15 Manufacture of ic chip mounting multilayer board Pending JPS6398189A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61243228A JPS6398189A (en) 1986-10-15 1986-10-15 Manufacture of ic chip mounting multilayer board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61243228A JPS6398189A (en) 1986-10-15 1986-10-15 Manufacture of ic chip mounting multilayer board

Publications (1)

Publication Number Publication Date
JPS6398189A true JPS6398189A (en) 1988-04-28

Family

ID=17100743

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61243228A Pending JPS6398189A (en) 1986-10-15 1986-10-15 Manufacture of ic chip mounting multilayer board

Country Status (1)

Country Link
JP (1) JPS6398189A (en)

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