JPS6398045A - Simulation system - Google Patents

Abstract

PURPOSE:To omit a work after linkage, and to reduce the number of processes, by providing an object memory part and a control memory part in one to one, in a cross type simulator. CONSTITUTION:Plural sets of the object memory parts 12 corresponding to the control memory parts 13 in one to one, are provided. In this way, it is possible to perform simulation by the level of a high-level language, loading and coupling the plural modules of compiled object level individually, on the object memory part 12. Therefore, it is possible to execute the simulation by the simulator 5 immediately after compilation. Thus, the work after the linkage can be omitted, and the number of processes of test debugging can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a software simulation method using a computer, and in particular, the present invention relates to a software simulation method using a computer. This article relates to a simieresi proverb system suitable for such cases.

[Conventional technology]

Conventionally, loss-type simulators, such as testing and puffing microprograms on large-scale computers, have used machine language as input, which has been assigned from a memory address, that is, a relative address, to an absolute address on the actual machine using a compiler. well known.

That is, the similation silane is performed according to the following procedure.

(1) Compilation (Assembling) Instruction words and register usage are generated as object code for each program, but memory addresses are assigned as temporary addresses.

Note that this applies to resolved names, and names in other programs (unresolved names) remain unknown.

(2) Collect linkage individual programs and assign temporary addresses to unresolved names. Integrate objects.

(3) Have the first absolute address of the locator-integrated object assigned (locator parameter), and determine each address as an absolute address.

(4) Code conversion Convert the load module to hexadecimal.

(5) Simulation Load The module is loaded into the simulation memory, the program counter is determined by a start command from the operator, and the simulation is started.

However, recently, due to the development using high-level languages and the increase in multitasking processing, development is often done without being aware of the absolute addresses on the actual machine, and in the same way, cross-type test knob bags are developed without being aware of the absolute addresses. It is important to be able to do this.

In multitasking processing, each task request performs program loading (memory allocation) and control transfer, so each task program is created so that it can be allocated anywhere in memory, and absolute addresses cannot be assigned. I'm not conscious of it.

Note that this technique is described in, for example, Japanese Patent Application Laid-Open Nos. 57-157357 to 56-90347.

[Problem that the invention seeks to solve]

The above conventional technology is based on PL/M of assembler language and high-level language.
To create a cross-minimized program written in , it is necessary to assemble or compile it to output object code, then use a linkage locator, code conversion, etc. For this reason, there are many work steps required to counter bugs, and it takes a lot of man-hours.Also, while the compile list during debugging outputs relative addresses, during simulation it outputs absolute addresses, and there are many cases where manual conversion using locator lists etc. is required, which requires man-hours. There is a problem.

The reason why the simulation is performed using absolute addresses is as follows.

Although there are pseudo-coating techniques that can be used at the source level, these techniques have not yet been established and there are many unknowns. Also, if the memory address is determined at the object level, it is sufficient to program the microcomputer H/W function (it is easy, and load modularization is always performed. Therefore, the simulator itself uses absolute addresses). It is efficient to develop a simulator in such a way that absolute addresses are not considered in the commands that operate the simulator.

Therefore, the purpose of the present invention is to provide a simulation system that reduces the number of man-hours required for testing and debugging microcontroller software by quickly taking measures against bugs (source correction, confirmation), etc., using a simulation using relative addresses that does not require linkage after compilation. The goal is to provide a simple method.

[Means for solving problems]

The above purpose is to provide a cross-type simulator with a simulator section that controls the input/output interface with the operator and the realization of microcomputer functions, an object memory section that stores relative address level instruction codes output by the compiler, and an object memory section. It consists of a control memory section for simulation control, which has a one-to-one correspondence with the computer, and a compile information analysis section that analyzes various information output by the compiler and creates symbol information, etc., and has multiple object memory sections and control memory sections. This is achieved by simulation at a high-level language level by loading and combining a plurality of individually compiled object code level modules into respective object memory sections.

[Operation] A cross-type simulator has multiple object memory sections and control memory sections, and loads multiple modules at the object code level that have been compiled individually into each object memory section and combines them at the high-level language level. Since it is possible to simulate
Simulation can be executed immediately after compilation.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

Note that this embodiment will be explained on the assumption that a program is written in the high-level language PL/M. FIG. 1 is a block diagram showing an example of the overall configuration for simulating microcomputer software on a large computer 1. As shown in FIG.

A compiler or assembler 3. under the operating system 2 in the large computer 1. Object analysis 4. There are various programs of the simulator 5, which are executed according to the following steps. Naori Rossimini Retalo is object analysis 4
and a simulator 5.

Step 1: Create an object file 8 from the source program 7 using the compiler/assembler 3.

Step 2: A test program file 9 is created by adding symbol information, etc. for test debugging at a high-level language level using the object file 8 using the object analysis 4.

Step 3: Input the test program file 9 and commands from the TSS terminal 10 or test file 11 to perform stain crystallization and shaking, and output the results to the TSS terminal 10 or test file 11.

This test file 11 is a storage file for a group of simulator operation commands (test start, interrupt setting, reference, etc.) and test input and output data.

If no synchronization is performed, it is created through link, locator, and code conversion programs at the same level as the compiler/assembler 3, although not shown.

FIG. 2 shows an outline of object analysis 4. The compiler 3 outputs the following information to the object file 8.

(b) Source list: A list in which statement numbers, structural nesting labels, etc. are added to the source program 7 coded by the programmer.

(b) Source expansion list: There is a list expanded in assembler language corresponding to the statement number (source) after optimization, and an instruction code converted from the assembly language into machine language code using relative address assignment. Note that the relative address assignment is divided into the instruction code part, constant part, and variable part, and is performed from the beginning of each part.

(c) Cross-reference list: All procedure names and variable names used in source program 7.

List of symbol information for label name, relative address, type (byte, word) for each symbol information.

Arrays, etc.), attributes (EXTERNAL, etc.), reference/update functions, etc.
Placement number? 1FIllO Renai Ai et al.@From the information in these object files 8, the object analysis 4 creates the following records in the test program file 9.

(b) Object: Sets machine language instruction code and constant code assigned by relative address.

(b)Mosier: A compilation unit program is called a module, and an information record regarding the procedures that make up the module. Module name.

Set the relative start and end addresses of the instruction code section, constant section, and variable section, the number of procedures in the module, and the entries for each record shown below.

(c) Procedure: Set information records regarding individual procedures including procedure name, relative start/end address, type, attributes, etc.

) Variable names; information records about individual variables.

Set variable names, relative starting addresses, types, attributes, structure information, etc.

(E) Statement number; statement number and assembler 71aEmWNtlU"JHJnmljJ7 i-1/
Fi? 1-1ff 71” Sumane◎ (to) Unresolved external reference name; information record regarding each symbol defined outside the module. That is,
Sets external variable names, external procedure names, and relative addresses of instruction codes that refer to these symbols to which relative addresses could not be assigned during compilation.

Based on the above information, SimijLator 5 is large computer 1.
Load as shown in Figure 3 above.

In FIG. 3, each part has the following functions.

ff, the simulator 5 controls the entire simulation, and in particular controls the entire function including the command words of the microcomputer. There are a plurality of object memories 12 corresponding to the number of modules to be simulated, and object record information is loaded therein. The control memory 13 is a simulation control information memory that has a one-to-one correspondence with the object memory 12, and is used for tracing, interruption, control during program migration between the object memories 12, and the like. The control table memory 14 develops each record information output by the object analysis 4 as a table corresponding to each module. Connections between each table are made by setting the start address during table expansion. The common memory 15 is a common memory for the microcomputer, and is used by the simulator 5 as interrupt vector table, stack memory, etc. Note that even if there are multiple modules, there is only one main memory. The program table 16 is a directory-like table for each module to be simulated, and is generated when a module is loaded. Here, the control memory 13 is a memory that has a one-to-one correspondence with the object memory, and is used exclusively for the simulator. For example, if you want to interrupt a program after it has run up to a certain step The interrupt control bit is set to 1. After that, when the program is started, the simulator always refers to the contents of the control memory 1 and interrupts if the interrupt control bit is 1. Therefore, the control memory 13 contains a statement like the one in the example. In addition to interrupt control by number, it also has a control bit for interrupting memory references and updates, and for indicating whether or not area initialization has been completed. This is memory reserved as

For example, an interrupt vector table (for H/W functions) with addresses 0 to 256 (1o) and a stack memory common to the system. Even if multiple programs are integrated, these systems remain one system and cannot be divided into multiple systems. In addition,
The interrupt vector table starts from address 0 and starts at the interrupt level (0
~63) This is an area for storing the processing branch destination address corresponding to 1o, and the stack memory is a memory for storing the return address at the time of an interrupt or a CALL instruction. Therefore, the number of loaded modules, the name of each module, the entry address of each module table, the instruction code section and
Addresses divided into constant part and variable part, common memory 15. Set the address of the control memory 13, etc.

Next, an example of simulation operation will be explained with reference to FIGS. 4 and 5.

FIG. 4 shows an example in which external variable name XYZ defined in module PYY18 is updated with procedure name AA of module PXX17, and FIG. 5 shows each memory relationship in the example of FIG.

tf, the simulator 5 is already loaded and the simulation is started from the procedure name AA.

The operator uses module PXX17. Load I'YY18 (LOAD command). The simulator 5 reads each record information from the test program file 9 and loads it onto the large computer 1 as shown in FIG. After loading, the control memory 13 is cleared, microcomputer functions are initialized (program counter, registers, etc.), and the process waits for the next operator input command.

Next, the operator causes the procedure master A of module PXX17 to start the simulation with a call through command.

It is assumed that the simulator 5 performs the following processing.

(a) Module PXX17. Refer to addressing program table 16 of procedure name AA and select module PXX1.
7, obtain the load addresses of the constant part, instruction code part, and variable part and the address of the module table.

- Bind the procedure table from the module table and detect the procedure name AA of the command input from the procedure table. The procedure table has a relative address of procedure name AA. Therefore, the above-mentioned (instruction code part load address) + (relative address of procedure name AA) dresses the object memory 12 seven times. Note that the relative address of this procedure name AA becomes the program counter on the microcomputer.

(Since the instruction word simulator Ill/program counter is determined as described above, the simulator 5 thereafter repeatedly executes instruction code fetch → decode → execution → increment of the program counter ().

Next, regarding control regarding external references, module PXX
Explain using the sentence 17°XYZ = 1234° as an example 6
(b) Extracting external reference names When a microcontroller fetches a move instruction between registers and memory, the instruction refers to the unresolved external reference table and updates or references the fetched program counter and unresolved external reference name. Compare with code relative address to get unresolved external reference name. In the example of FIG. 4, the variable name XYZ is an external reference name in module PXX17 and is unresolved, and is registered in the unresolved external reference table.

Therefore, it can be recognized that the variable name XYZ may exist elsewhere.

(b) Addressing external reference names Other modules, that is, module PYY in the example in Figure 4
18, program table 16 → Moji x Lua”
-Full→Refer to the variable name table and each table of Mosier PYY18 to obtain the relative address of variable name XYZ.

Note that the addressing is not the load address of the variable part of the module PXX17 in operation, but the address of the program table 16.
When referenced, the result is (variable part load address of Mosier PYY18) + (relative address of variable name XYZ).

(c) Simulation of instruction word Writing is performed using the variable part address mentioned above. After that, I will continue with the simulation of Mosier PXX17.

Although an example of operation in this embodiment was explained, the module PXX
When program control is transferred between object memories 12, such as by calling the procedure name of module PYY18 using the C'AI and L instructions of 17, the reference table is the call table - program table 16 -> module table -> procedure table -> unresolved. Since it becomes an external reference table and program control changes, each load address is changed from module PXX17 to the constant part of module PYY18.
The difference is that it is changed to the load address of the instruction code section/variable section.

Although this embodiment describes the case where the simulation is executed on a large-scale computer, it can also be executed on a normal computer or the like.

Simulations can be similarly executed using a processor such as a workstation or a personal computer.

According to this embodiment, a plurality of object memories 12 115
Since each module after compiling can be loaded individually and simulation can be performed using the control table memory 14, it is possible to debug a test by omitting work such as linkage, and ultimately reduces the number of man-hours for testing and debugging.

Also, in the compile list when analyzing errors,
°The address on the memory layout matches the module address, so it is easy to deal with it.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, multiple programs can be combined and simulated at the object level after compilation, so work after linkage can be omitted, and the cycle from bug fixing to confirmation can be shortened. This has the effect of increasing speed and improving testing and debugging efficiency.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the overall configuration of the cross-miniature radio controller of the present invention, and FIG. 2 is a diagram for explaining the outline of the naopji construction analysis required to perform high-level language level simulation in FIG. 1. , Fig. 3 is a diagram for explaining the configuration mainly including memory arrangement during the first simulation run, Fig. 4 is a diagram showing an example of the P L /M language, and Fig. 5 is a diagram for explaining the operation. FIG. 3 is a diagram showing table relationships. 1... Large computer, 3... Compiler/assembler, 4... Object analysis, 5... Simulator, 8... Object file, 9... Test program file, 12... Object memory, 13...Control memory, 14...Control table memory, 15...Shared memory, 16...Program table d 2nd month 3rd close

Claims (1)

[Claims] 1. In a software simulation method using a computer, a simulator section that controls input/output interfaces and software realization, an object memory section that stores relative address level instruction codes output by the compiler, and a simulator section that corresponds to the object memory section. It is composed of a control memory section for simulation control, and a compile information analysis section that creates information according to various information output by the compiler, and has at least one object memory section and one control memory section, and has at least one object memory section and one control memory section. A simulation method characterized in that a plurality of compiled object code level modules are loaded into each of the object memory sections and simulated while being combined.