JPH0695921A - Simulation method and program debugging system - Google Patents

Abstract

PURPOSE:To speed up processing in the case of simulating or debugging the execution of a program for a target computer by a host computer. CONSTITUTION:A compiler 2 generates an object information program 6 from a source program 1 for the target computer. The program 6 is obtained by translating instruction strings (including no jump instruction, branch instruction, or restoring instruction from a subroutine on the way) for the target computer which can be sequentially executed into instruction strings for the host computer 3. Since simulation is executed in each translated instruction string, the convensional overhead of instruction interpretation as data for the execution of one step can be reduced and the speed-up of simulation can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulation method and a program debug system, and more particularly to a technique effectively applied to a simulator debugger for debugging a program of a target computer on a host computer.

[0002]

2. Description of the Related Art A conventional simulator debugger or simulator has instructions of a target computer as data, and interprets and executes each instruction (one step execution).
The goal of the simulation was achieved by doing. That is, since the execution environments of the target computer and the host computer are significantly different, including the CPU (Central Processing Unit), the simulator expresses the execution environment of the target computer by software, receives the machine language of the target computer as data, and gives instructions. Interpret in units and realize the corresponding operation in a pseudo manner. Such a method is hereinafter referred to as an interpreter method. In addition, in order to perform debugging at a high-level language level using the simulator debugger, the variables and source line numbers specified in the high-level language and corresponding information such as the address and size of the object program are stored as data. The necessary operation for debugging was performed by interpreting, that is, searching and referencing. For example, this operation is an operation such as acquisition of the variable address of the source program necessary for reference at the time of debugging, acquisition of the address of the target program from the line number of the source program, and the like. In addition, as an example of the document describing the simulation, November 3, 1984.
"LSI Handbook" issued by Ohmsha on the 0th
There is page 561.

[0003]

However, in the interpreter type simulation, since the instruction code of the target computer is received as data and is interpreted in the instruction unit to simulate the corresponding operation, the overhead of the interpretation execution of the instruction code causes the target. There is a problem that it becomes significantly slower than execution on a computer. Also,
The debugging function at the high-level language level has been designed by providing a rule for debugging information for each language and interpreting and executing the debugging information for debugging. With this method,
Not only does the execution speed decrease because processing such as a table search of data related to debug information is required, but it is also necessary to establish a debug information convention for each high-level language for writing the source program of the target computer. It was necessary to incorporate the above process into the simulator debugger in advance. This significantly impairs the versatility of the simulator debugger.

An object of the present invention is to simulate execution of a program for a target computer on a host computer,
Furthermore, it is intended to speed up the processing when debugging. Another object of the present invention is to realize a function capable of being debugged by the same simulator debugger regardless of the type of high-level language that describes the program to be debugged.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, in the conventional method, the instruction of the target computer is received as data, and the instruction is interpreted and executed one by one during the simulation. However, in the present invention, the instruction sequence of the target computer that can be sequentially and sequentially executed, that is, in the middle. An instruction sequence that does not include a jump instruction or branch instruction, or a return instruction from a subroutine, and does not include a branch destination instruction of these instructions is translated into the instruction sequence of the host computer in advance before the simulation, and this translated Simulation is performed with the instruction sequence as a unit. This reduces the overhead of the conventional instruction interpretation accompanying the simulation of each instruction. The same overhead reduction method is also applied to the interpretation of debug information for debugging the target computer program. In other words, the compiler prepares the correspondence between the information corresponding to the concept on the source program and the information corresponding to the concept on the hardware resource on the target computer as a debug operation procedure expressed by the instruction of the host computer. , It enables debugging at a high-level language level by calling this debugging operation procedure as needed. At this time, since the operation to be executed is directly described in the machine language of the host computer without requiring a special interface for interpretation and execution, the high-level language specifications of the target computer can be specified especially in the operation for debugging. It realizes debugging at a high-level language level without depending on it. Here, the target computer referred to in this specification is not limited to a so-called computer, but can be set and changed, and a hardware resource whose state can be expressed by the hardware of the host computer and a basic operation for the resource are described. Any device you have will do.

Next, the details of the above means will be individually described for each item.

(1) Acceleration of Simulation Acceleration of simulation is realized by the following means. (A) For the hardware resources such as the memory, registers and flags of the target computer, the memory of the host computer,
Registers and flags are associated with each other so that the internal state of the target computer can be faithfully represented by the internal state of the host computer. That is, the execution environment of the target computer is expressed by the resources and software of the host computer. (B) For each instruction of the target computer, the instruction sequence of the host computer that simulates the action of the instruction on the host computer associated with the hardware resource of the target computer is associated. (C) A basic block of the program of the target computer (an instruction sequence that is always executed sequentially, that is, an instruction that does not include a jump instruction, a subroutine instruction, or a return instruction from a subroutine in the middle, and does not include a branch destination of the instruction. Column) is cut out, and a sequence of instruction sequences of the corresponding host computer is generated. By this and the above item (b), the instruction sequence of the host computer obtained by translating the instruction sequence of the target computer that can be executed sequentially is acquired. (D) The data flow of the generated instruction sequence of the host computer is analyzed and optimized. (E) A table is created in which the start address of the basic block of the target computer is associated with the instruction string of the host computer corresponding to the basic block. (F) The execution of the basic block of the target computer is simulated by executing the instruction sequence of the corresponding host computer. (G) The execution of the jump instruction or the branch instruction of the target computer is simulated by transferring control to the instruction sequence of the host computer corresponding to the address of the jump or branch destination.

(2) Switching of simulation function When all simulations are performed by the above method, a breakpoint function, an instruction rewriting function, which is a part of the basic simulation function, and a function of jumping into a basic block during debugging are performed. It will be a sacrifice. In order to avoid this, the above method and the conventional interpreter method or the one-step execution method are used together, and a switching method that can speed up the simulation function without reducing the size is realized by the following means. (A) A flag indicating the designation of a breakpoint is provided for each basic block, and if the breakpoint is designated in that basic block, the target is transferred without transferring control to the instruction sequence of the corresponding host computer. Switch to interpret and execute the computer one instruction at a time. (B) When an instruction is rewritten during debugging, the basic block including the instruction is translated again to update the correspondence between the instructions of the target computer and the host computer. In addition, when the basic block is divided by rewriting the instruction (change to the instruction jumping into the basic block, etc.), the new divided basic block is also translated. (C) When an address other than the start of the basic block is specified by the execution start address specification during debugging, the basic block is simulated for each instruction by the conventional method, and the subsequent basic blocks are simulated by the above method. To do.

(3) High-level language level debug function realized by host computer instructions The high-level language level debug function uses the information (variable name, line number, etc.) corresponding to the concept on the source program in the target computer. Corresponds information (address value, register name, etc.) corresponding to the above concept of hardware resources. These correspondences are realized as a procedure expressed by a command of the host computer. This is done by the following means. (A) When the source program is compiled, a procedure for debugging the host computer is generated. For example, if you want to obtain the allocation address value from the variable name, enter the variable name and the current program counter value, and return the variable allocation address at the program point corresponding to the program counter as a result Generate as. (B) The simulator debugger realizes the debug function by loading the above-mentioned debug procedure as a program of the host computer when loading the program of the target computer and directly calling the debug procedure.

[0012]

According to the above means, the simulation is performed using the instruction sequence of the host computer translated in advance corresponding to the basic block of the target computer, and the debugging operation procedure expressed by the instruction of the host computer is used. Performing debugging by eliminating the overhead of data interpretation such as the conventional interpretation of object code given as data and the search reference of the data table for the debug operation procedure speeds up simulation and debugging. To be realized.

Further, by performing the debugging by using the debugging operation procedure expressed by the instruction of the host computer, the high-level language debugging function can be easily incorporated in the simulator debugger without depending on the high-level language. To

[0014]

1 is a block diagram of a simulator debugger according to an embodiment of the present invention. In the figure, reference numeral 1 is a source program written in a high-level language for the target computer. This source program 1 is a target for simulation and debugging. The source program 1 is compiled by the compiler 2. The compiler 2 converts the source program 1 into an object code 4. Conventionally, the object code 4 is given to the host computer 3 as data and the simulation is performed in units of one instruction. In this embodiment, the compiler 2 generates a debug information program 5 and an object information program 6.

As will be described in detail later, the object information program 6 is a set of blocked instruction sequences formed by translating the instruction sequences of the target computer that can be executed sequentially into the instruction sequences of the host computer 3. Is. Therefore, an instruction that changes the instruction execution flow or the order of instructions to be executed, such as a jump instruction (JMP instruction) to a subroutine or a return instruction (RTS instruction) from a subroutine, is included in the middle of the translated instruction sequence. I can't. The debug information program 5 debugs the correspondence between the information corresponding to the concept on the source program 1 and the information corresponding to the concept on the hardware resource on the target computer (not shown) expressed by the instruction of the host computer 3. It was compiled as a user operation procedure. The debug information program 5 and the object information program 6 are composed of instruction descriptions suitable for the host computer 3, and are linked to the simulator system program 7 positioned as the core of the simulator as required and loaded into the host computer 3. The host computer 3 simulates the source program by executing the loaded program in accordance with the command and supports debugging.

The processing procedure by the simulator debugger according to the present embodiment will be described in detail in the order of items with specific examples.
For the purpose of simplifying the explanation, a concrete example of the simulator part will be described assuming that the host computer and the target computer have the same instruction specifications, but it is actually useful when the host computer and the target computer are different. Is. In any case, there is no difference in operation principle. In the description of the processing that does not directly depend on the instruction of the host computer, the C language is used as the high-level language.

(1) Correspondence of hardware resources It is assumed that each of the host computer 3 and the target computer (not shown) has eight general-purpose registers (R0 to R7), a status register (SR), and a program counter (PC). . The word size is 4 bytes, and the addressing is performed in byte units. In this embodiment, general-purpose registers, status registers, and
The program counter is associated with the memory of the host computer 3. The following memory areas are allocated in the host computer 3 to the hardware resources of the target computer. unsigned long general_reg [8]; General register area unsigned long status_reg; Status register area unsigned long program counter; Program counter area unsigned long memory [MEMORY_SIZE]; Memory area Here, the target computer register is the memory of the host computer 3. The purpose of the assignment is to more clearly present the following explanation, and of course, by allocating the register of the target computer to the register of the host computer, faster simulation becomes possible. In this case, it is necessary to save and restore the register at the time of accepting the simulator command and at the time of simulation.

(2) Translation of Target Computer Instructions An example is shown in which target computer instructions are translated into host computer 3 instructions one-to-one. Example 1: An example of translation of the instruction "MOV R0, R1" is shown. This instruction transfers the contents of register R0 to register R1,
The instruction size (4 bytes in this example) is added to the program counter. Therefore, the following host computer instructions correspond. MOV @general_reg, @ (general_reg + 4) ADD # 4, @ program_counter Example 2: A translation example of the instruction "ADD R0, R1" is shown. This instruction transfers the contents of register R0 to register R1,
The calculation result is reflected in the status register, and the instruction size (4 bytes in this example) is added to the program counter. Therefore, the following host computer instructions correspond. ADD @general_reg, @ (general_reg + 4) MOV SR, @ status_reg ADD # 4, @ program_counter Example 3: A translation example of the instruction "BRA 10" is shown. Such a branch instruction becomes the last instruction of the basic block. This instruction sets the value of the program counter to 10. In this case, the command of the host computer 3 shown below is supported. MOV # 10, @ program_counter Similarly, the rules for translating each instruction are determined, and the instruction sequence of the host computer is generated for each basic block of the target computer according to the rule.

(3) Optimization of host instruction sequence Since the translated instruction sequence of the host computer 3 has no control transfer (because it does not include an instruction such as a jump instruction or a branch instruction on the way), It can be optimized by tracking movements. This is an application of a general technique called copy propagation in compiler technology, but it is new to apply this optimization technique to the translated instruction sequence of the host computer for simulation. Example 1: Consider the target computer instruction sequence: MOV R0, R1 MOV R0, R2. According to the rule of the above item (2), this is translated into the following instruction sequence. MOV @general_reg, @ (general_reg + 4) ADD # 4, @ program_counter MOV @general_reg, @ (general_reg + 8) ADD # 4, @ program_counter The above instruction sequence is replaced with the following instruction sequence that performs the same function by optimization. Is possible. As the optimization contents,
The contents of the register R0 of the target computer are assigned to the register R0 of the host computer 3, and the two updates of the program counter are combined into one. MOV @ general_reg, R0 MOV R0, @ (general_reg + 4) MOV R0, @ (general_reg + 8) ADD # 8, @ program_counter Example 2: Consider the target computer instruction sequence ADD R0, R1 ADD R0, R2. According to the rule of item (2) above, this is
It is translated into the following command sequence. ADD @general_reg, @ (general_reg + 4) MOV SR, @ status_reg ADD # 4, @ program_counter ADD @general_reg, @ (general_reg + 8) MOV SR, @ status_reg ADD # 4, @ program_counter The above instruction sequence is as follows: Can be optimized. Here, in addition to the optimization contents of the above-mentioned example 1, two updates of the status register are optimized to one update. MOV @ general_reg, R0 ADD R0, @ (general_reg + 4) ADD R0, @ (general_reg + 8) MOV SR, @ status_reg ADD # 8, @ program_counter

(4) Loading the host instruction sequence into the simulator The instruction sequence generated by the optimization in item (3) above is loaded during simulation. The loading is performed when the debug target program (object code 4) of the target computer is loaded as data into the host computer 3 of the simulator debugger. A subroutine return instruction (RTS) can be added to the end of the instruction sequence to be executed last in the loaded plurality of host instruction sequences.
As a result, the basic block of the program of the target computer can be simulated by starting the subroutine in the host computer 3.

(5) Execution of simulation by host instruction sequence The simulation is executed by the host instruction sequence by the following procedure. simulate () {for (;;) simulate_block (); Basic block simulation} simulate_block () {void (* f) (); f = get_host_action (program_counter); Get start address of host instruction string (* f) ( ); Execution of host instruction sequence} FIG. 2 shows a flowchart of the execution procedure. According to FIG. 2, the simulation for each basic block is roughly divided into a PC value acquisition step (S1), a translated code retrieval step (S2), and a translated code execution step (S3). . The PC value in the PC value acquisition step is the start address of the basic block in the program of the target computer (on the source program), for example, the parameter of the command or the jump destination of the jump instruction in the simulator system program of the host computer 3. Given as an address. In the step of searching the translated code, the correspondence table between the start address of the basic block and the start address of the corresponding translation instruction string is searched, and the PC obtained in step S1 is searched.
The start address of the translation instruction sequence on the host computer 3 corresponding to the value is acquired. In step S3, the translation instruction string whose start address has been searched is sequentially executed to the end. The processing for each instruction is instruction fetch, instruction interpretation, and instruction execution, and jump instructions and branch instructions are not executed in the middle. Incidentally, in FIG. 2, A is P which the host computer 3 has as a resource of the target computer.
The value of C (program counter) is shown, and B means the start address of the corresponding translation instruction string block. FIG. 3 schematically shows a process transition in executing the JMP instruction. In the figure, 61 to 67 are blocks of a translation instruction string corresponding to basic blocks, respectively. According to FIG. 3, at the end of the block 62 of the translation instruction sequence, an instruction for setting the branch destination address 100 in the PC and an RTS instruction for returning from the translation instruction sequence are arranged as a result of translating the JMP instruction. ing. When the host computer 3 executes the RTS instruction at the end of the translation instruction sequence block 62 in the simulation, the jump destination is processed by the PC value acquisition step S1, and then the corresponding translation is performed in the translated code retrieval step S2. The start address of the instruction string block, for example 66, is obtained, whereby the processing routine instructed by the JMP instruction is simulated by executing the translation instruction string block 66. The processing when the RTS instruction is arranged at the end of the instruction string block to be translated is similar to the above.

(6) Realization of Debug Function In the simulation of the translation instruction string unit of the host computer 3 for the basic block, the inside of the basic block of the program to be debugged cannot be operated. Therefore, the conventional one-step execution method for interpreting and executing each instruction is used in combination with the method of the present embodiment, and a detailed debug function is realized as follows.

(7) Realization of Breakpoint When a breakpoint is specified inside the basic block, a flag corresponding to the basic block is set, and when the flag is set, the basic block is set to the conventional 1 Interpretation is executed for each instruction in the step execution method. This is achieved by the following procedure. simulate_block () {void (* f) (); if (get_flag (program_counter)) Judge the flag simulate_step_by_step (); Conventional simulation else {f = get_host_action (program_counter); New simulation (* f) (); } FIG. 4 shows a flowchart of the execution method. According to the figure, the presence / absence of a breakpoint is determined, and if it is specified, the simulation is performed in one step execution. If it is not specified, the execution form by the translated code as described with reference to FIG. 2 is executed. Simulate with.

(8) Execution from the middle of the basic block Even in the middle of the basic block, similar to the case of the item (7), the basic block is simulated by the conventional method, and the basic block to be executed next is updated. Switch to method simulation.

(9) Change of instruction during debugging When an instruction is rewritten during debugging, the basic block is translated into a host instruction sequence again, and a new host instruction sequence is reregistered with the start address of the basic block. .

(10) Change of basic block configuration at the time of debugging When an instruction is rewritten to a branch instruction at the time of debugging, a new basic block is generated. In this case, not only the basic block including the rewritten instruction but also the basic block including the jump destination of the rewritten branch instruction are retranslated and reregistered if necessary.

(11) Realization of high-level language debug function by host computer command word An example of realizing a high-level language debug function by a host computer command word is shown below. Hereinafter, the C language is used to express these functions, but in reality, a machine language host computer instruction sequence corresponding to a procedure described in the C language is generated and used by the compiler 2.

(12) Acquisition of Variable Address It is necessary to acquire the address of the variable in order to set or refer to the variable in the high-level language during debugging. Since this address can be determined at the time of compiling, when the compiler 2 compiles the debug target program, at the same time, the following procedure is generated as an instruction of the host computer 3 and dynamically loaded at the time of debugging. void * get_address (char * var) {if (strcmp (var, "a") == 0) Check variable name if (program_counter> = 100 && program_counter <200) Check program counter value return & memory [200]; :: else return NULL;:: else return NULL;} The procedure as shown above, as shown in FIG.
The variable name known at compile time is compared with the variable name given at debugging, and if the variable names are the same, the range of the program counter in which the allocation of each variable is constant,
This is a procedure for comparing the current program counter value and obtaining the address of the variable in the current simulation situation. In this procedure, anything other than those given as parameters can be determined at compile time. Therefore, it is possible for the compiler 2 to generate this procedure. By loading and calling these procedures for the host computer 3, the debugger can set or reference the value of the variable at the time of simulation at a high level language level without providing a special convention for debug information.
The special convention for debug information in traditional debuggers is
It is a convention for data interpretation such as data retrieval and reference, depending on the language of the source program of the target computer. A similar procedure is provided for basic operations of high-level language level debugging, such as the acquisition of the program counter value of the program point corresponding to the line from the line number, to realize the high-level language level debug function independently of the language. You can In addition to this procedure, there is a procedure for obtaining the address of the target program from the line number of the source program and vice versa.

(13) High-level language level debugging when multiple modules are linked When multiple modules are linked, multiple debugging procedures can be performed. This can be realized by providing each module with a table holding the entry address of the procedure of the basic bag operation at the high level language level. By the processing of such a link, a program as a unique host computer instruction sequence for desired simulation and further debugging can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. Yes. In the above description, the case where the invention made by the present inventor is mainly applied to the simulator debugger which is the field of application which is the background has been described. However, not only the simulator but also the system debug of an unfinished microcomputer application system and the system thereof are described. It can also be applied to systems and methods for emulating the debugging of target programs for. The present invention can be widely applied to the condition that at least the instruction of the target computer and the procedure information for debugging are compiled into the native code of the host computer and used.

[0031]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) A simulation is performed by using the instruction sequence of the host computer translated in advance corresponding to the basic block of the target computer, and the debugging is performed by using the debug operation procedure expressed by the instruction of the host computer. By doing so, it is possible to eliminate the overhead for data interpretation such as the interpretation of the object code given as data and the search reference of the data table for the debug operation procedure as in the past, and to realize the speedup of simulation and debugging. it can. (2) With the above, the range of programs to be debugged can be greatly expanded. Therefore, it becomes possible to debug a large-scale system using a simulator, which was difficult with the conventional method. (3) By combining the simulation method and the conventional interpreter method (one-step execution method) and switching the simulation method, a breakpoint function, an instruction rewriting function, a function to jump into a basic block during debugging, etc. Without sacrificing
In other words, the simulation can be sped up without reducing the simulation function. (4) A simulator or a simulator debugger that does not depend on the type of high-level language can be realized by performing debugging using the debugging operation procedure expressed by the instruction of the host computer. (5) By the above (4), the debug function can be realized without changing the simulator even when a new language appears. (6) With these, it is possible to realize high-speed debug command execution and a program debug system that does not depend on the language specifications of high-level languages.

[Brief description of drawings]

FIG. 1 is a block diagram of a simulator debugger according to an embodiment of the present invention.

FIG. 2 is a flowchart of a high-speed simulation execution method.

FIG. 3 is an explanatory diagram schematically showing a process transition in JMP instruction execution.

FIG. 4 is a flowchart for explaining a breakpoint realization method.

FIG. 5 is a flowchart illustrating an example of processing by a debug information program, which is an example of variable address acquisition.

[Explanation of symbols]

 1 Source Program 2 Compiler 3 Host Computer 4 Object Code 5 Debug Information Program 6 Object Information Program 61-67 Translation Instruction Sequence Block 7 Simulator System Program

Claims (6)

[Claims] 1. A simulation method of translating an instruction of a target computer into an instruction of a host computer, loading the instruction into a host computer and executing the instruction, wherein an instruction sequence of a target computer that can be sequentially and sequentially executed is stored in the host computer. A translation step of translating into an instruction sequence, a correspondence step of associating a start address in the instruction sequence of the target computer with a start address in the translated instruction sequence of the corresponding host computer, and Simulating the execution of the instruction sequence of the target computer by executing the instruction sequence of the corresponding host computer based on the determined correspondence. 2. The simulating step includes a step of acquiring a start address of a predetermined instruction sequence of a target computer, and a start address in an instruction sequence of a corresponding host computer based on the start address obtained thereby. 2. The simulation method according to claim 1, further comprising: a step of searching and a step of sequentially executing an instruction string of the host computer from the searched start address. 3. A jump or branch instruction included at the end of the instruction sequence of the target computer is simulated by shifting execution to the instruction sequence of the host computer corresponding to the jump or branch destination address. The simulation method according to claim 1 or 2, characterized in that. 4. A step of determining whether or not a breakpoint is designated, wherein when a breakpoint is designated, the instruction sequence of the host computer is not executed and the instruction of the target computer is sequentially interpreted as data 1 4. The simulation method according to claim 1, wherein the simulation is performed by step execution, and when there is no instruction of a breakpoint, the instruction sequence of the host computer is executed to perform the simulation. 5. A correspondence between information corresponding to the concept on the source program and information corresponding to the concept on the hardware resource on the target computer is generated as a debugging operation procedure expressed by an instruction of the host computer. A compiler, and a simulator debugger that loads the debug operation procedure and enables debugging at a high-level language level by calling the loaded debug operation procedure as needed. And a program debugging system. 6. The simulator debugger sequentially translates an instruction sequence of a target computer that can be sequentially executed into an instruction sequence of a host computer, a start address in the instruction sequence of the target computer, and the corresponding addresses. A simulation is performed by executing the instruction sequence of the target computer based on the correspondence between the head address in the translated instruction sequence of the host computer and the instruction sequence of the corresponding host computer. 6. The program debug system according to claim 5, wherein: