JPS6395737A - Data transmission system - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to data transmission systems, and more particularly to channel coding within data transmission systems.

In recent years, much interest has been focused on channel codes that achieve so-called coding gain. Among these, one to be particularly careful about is the so-called "trellis".
"Channel coding with multilevel/phase signals (Channel Coding with Multilevel/Phase Signals)
el Coding With Multilevel
/PhaseSignala)], IEEE
Transactions of Information Seven Ori, IT-28 (IEtEETrans, Info
rmation Theory+ IT-28) s page 55-67, A, R, Calderbank (A, R
.

Calderbank) and N. J. A. Sloan (N.
, J.A.

5loane) paper [A New Family of Codes for Dial-up Voice Lines]
y ofCodes for Dial-Up Voi
ce Lines), IEEE International Cloud Communications Conference Article 4 (Proc, IEEE Global
Telecomm, Conf, ), 1984 1
January, pages 20.2.1-20.2.4i A, R, Calderbank and N, J, A, 5loane
) paper [4-dimensional modulation using 8-state lattice code (
Four-Dimensional Modulation
With an Eight-State Tre
llis Code)], AT&T Technical Journal (8T&T Technical Journal
1), Vol. 64, Kan 5. May-June 1985, Pages 1005-1018;
.

Sloane's paper [An Eight-Dimensional Lattice Code (An Eight-Dimensional Lattice Code)]
sional Trellis Code)], IE
EE Articles, Vol. 74, 5. 1986, pages 757-759; Andori, F., Wei (L.).

F, Wet) paper [Rotationally Invariant Convolutional Channel Coding with Extended Signal Space - Bart I: 180 degrees and Bart ■: Nonlinear Codes (Rotationally Inv.
ariantConvolutional Chan
nel Coding With Expande
dSigal 5pace-Part I
: 180 Degrees and Part II
: Non1inear Codes ) ] , I
IEEE J, Selected Area Communication (IEEE J, 5e
lect, Areas Commun, ), Vol.
, S A C-2, September 1984, page 659-
See 686. Commercial use of these codes is focused for the most part on voice band data sets and other carrier data systems. However, it is desirable to also use these codes in baseband systems, such as local area networks and central office switching systems. However, an obstacle to the use of lattice codes in base band systems is that the encoded signals produced by conventional lattice coding techniques have a significant component at dc. This is problematic from many points of view. For example, transformer coupling that is required or at least desired in many applications cannot be used because the transformer does not bus dc. Additionally, transmission errors may occur if the remote signal's ground reference is not accurate. Furthermore, if we include the signal power in da,
Loss of signal power occurs in most detector configurations.

The present invention provides line signals for implementing grid codes in systems where the presence of a large amount of DC acid components is a problem.
- As an example, at dc the spectral null
) regarding lattice coding technology. In the present invention,
At least one of the signal points to be transmitted is determined not only as a function of the grid-seeded input bits but also as a function of a running value that is a function of the components of previously transmitted signal points. .

In an exemplary embodiment of the invention, (k+n)
- Output signal points representing bit input words are generated. The value of the n bits of each input word and the value of at least one bit of the previous input word are determined by a signaling alphabet (sign
used to identify a particular one of 211 subsets of the aling alphabet). Here, m
> n. Other bits of the input word identify multiple signal points of the identified subset. - As an example, this other bit identifies a pair of signal points, where the sum of the components of one signal point of each pair is greater than or equal to some predetermined value, and where the sum of the components of one signal point of each pair The sum of the components is less than or equal to this predetermined value. At any point in time, the lining value above - for example, the lining sum of the components of the previously transmitted signal points (runni
If ng su+w ) is larger than this predetermined value, then
Identified pairs of signal points whose component sum is less than or equal to this predetermined value are generated. Conversely, if the lining sum is less than or equal to this predetermined value, an identified pair of signal points whose component sum is at least equal to this predetermined value is generated. In this exemplary embodiment, this predetermined value is zero. Therefore, if the component sum is greater than or equal to zero, a signal point whose component sum is less than or equal to zero is generated. As will be explained in detail later, the method uses a channel with a spectral null at dc.
Provide a coded signal.

Encoder 10 of FIG. 1 receives data from a data source 9 in the form of a serial bit stream. This bit stream is applied to a serial/parallel (S/P) converter 11, which produces a sequence of (k+n)-bit words. - As an example, assuming k=4 and n=2, converter 11 generates these 6-bit words in parallel on 1-bit leads 12a-d and 13a-b. Four of these bits appear on leads 12a-d and the other two bits appear on leads 13a-b. lead 1
The sequences of input words on 2a-d and 13a-b are processed as explained in detail below. However, at present, in response to these input words, the lattice point (l
Note that the generator 20 generates four-dimensional points, ie, 4-tuples taken from a lattice of odd integers.

The individual components of the individual grid points thus generated appear on a corresponding one of the four multi-bit leads '1la-d. The individual grid points on leads 21a-d are sent to a sign (sigr+) inverter circuit 35. The circuit 35 operates under the control of the lining summation circuit 35 to pass through the grid points unmodified or to invert the sign of the individual components to produce different points in the grid.

The outputs on multiple bit leads 25a-d of circuit 35 represent the signal points to be transmitted.

A sequence of output signals, each representing one of the signal points to be transmitted, is then immediately generated and applied to the desired transmission channel. More specifically, the lead 25a
The signal points on -d are applied to a parallel/serial (P/S) converter 40 which produces a serial bit stream on encoder output lead 45. This bit stream of 0's and 1's is applied to a conventional baseband pulse generator 50, which generates a baseband line signal suitable for transmitting these 0's and 1's through a transmission channel. do.

Each of the four components of the signal point in this implementation is 4
It takes one value: 1, -, 3, -3. - As an example, these signal points are (1, 3, -3, ■) and (
-3, 3, 3, -3). Therefore, the alphabet of signal points has 4'=256 elements. This alphabet is divided into 2n subsets, by way of example.

Here, m>n. Assuming m=3, 23=8
There exists a subset of , whose alpha vents are 2 (k
+m+I) signal points.

To HM 'J- into this subset, the 4-tuple is first 16 Bart S (el, e2, e3, e
4). Here, ei=Q or 1. In other words, these 16 parts are 5 (0000), S (0
001) , S (0010) , etc. A certain 4-tuple (xi, x2, x3, and x4) is a certain vert 5 (el, e2, e3, e
It belongs to 4). So, for example, for a particular 4-tuple, the first two elements of the 4-tuple are component +
It matches (-1) o (modulo 4) that includes 1 and -3, and the other two components of this 4-tuple are -1 and +3
If it matches (-1) l (modulo 4), it belongs to part 5 (0011). Therefore, 5(00
11) includes the following 16 elements.

(-31-1-1> (1-3-13) These 16 parts are then divided into m=8 subsets as follows.

S,=S(0000)U 5(1111) 5S=S
(0001) U 5 (1110) sz=s (0011)
u 5 (1100) 56=S (0010) U' 5
(1101)S,=S(1010)U 5(0101)
S,=S(0100)U S(1011)S,=S
(1001) U 5 (0110) S, = S (100
0) U 5 (0111) Here, the symbol U is “union”
ion of)''.In other words, the subset S
2 contains the 16 4-tuples of Burt 5 (0011) listed above plus 16 4-tuples obtained by reversing the sign of the individual components of this part. - As an example, table ■ is subset S1,
The elements of S2 and S3 are shown with their respective subsets subdivided into two halves. More specifically, one half of each subset, indicated by the superscript "+", contains all points for which the sum of the components is a positive number, and the other half, indicated by the superscript "-" includes all points whose components sum to a negative number. Each point where the sum of the components is zero is arbitrarily assigned to one of the two halves.

(In this table, “-” and “-3” are shown as “T” and “D” respectively for the purpose of space constraints.) Table ■ 0000 (1111) (Tai11) (1
111)0101 (3311) (Ω11)
(3131) S z S s+S e (!131) (3311) (3311) Returning again to FIG.
is coder) 15. Lead 13a-
The two bits on b are sent to lattice encoder 15 and encoder 1
5 is divided into eight subsets S in a manner that will be explained in detail later.
Identify a specific one from 1 to 88. The encoder 15 is therefore a so-called rate 2/3 lattice encoder. Assuming that there are 2S-32 signal points in each subset, S/P converter 11 would transfer 5 bits to ROM 17 if it had a conventional lattice encoder configuration.
in addition to 3 in the subset in which these 5 bits were identified.
Used to identify a particular one of two signal points.

However, according to the invention, one input word with fewer than five bits is applied to the ROM to identify signal points within this subset. More specifically, only four bits on leads 12a-d are added to ROM 17 and these bits are used to identify a particular pair of signal points within the identified subset. (As explained below), this particular pair of signal points is identified by producing one of the two signal points of the pair on ROM output leads 13a-d.

) In this embodiment, the signal points are defined within each subset as the sum of the components of the signal of one of the two signal points of the pair, i.e. the arithmetic sum of the components is equal to the sum of the components of the other signal point of the pair. are paired so that they are opposite. The individual pairs of points are located adjacently in Table I. Indeed, in this embodiment, individual signal points within a pair can be extracted from the other of the pair simply by inverting the sign of the individual components.

- As an example, subset S2 consists of signal point pairs (3
, 3, -3, 1)/ (-3, -3, 3, -1), and these components add up to 4 and -4, respectively. However, in the broader aspects of the invention, it is sufficient that the component sum of each pair of signal points is at least equal to a predetermined value N, and that the other component sum of the signal points is less than or equal to N.

The assignment of 4-bit word values to signal point pairs can also be arbitrarily assigned to individual subsets. However, in this embodiment, the allocation ratio is 12a-
This is done so that each of the 16 possible combinations of "0" and "1" on d is assigned to a particular pattern of "1" and "3" through all subsets, ignoring the sign.

Thus, for example, as shown in Table 3, the bit pattern 0000 corresponds to all points whose individual components are 1 or -l.

To determine which signal point of the identified pair should be output by the encoder 10, a lining value is maintained that is a function of the components of the signal points previously generated by the encoder. This lining value is, for example, the lining sum. If at any point in time this lining value is greater (less than) O, then
The encoder outputs signal points of the identified pairs whose component sum is smaller (larger) than O, making the lining value less positive (negative). If the lining value is zero, or if the sum of the components of the individual points of the identified pair is zero, then the encoder outputs any one of the signal points of the identified pair. Therefore, if the lining value is already non-zero, it will be driven towards zero. (More generally, if at any point in time the lining sum is at least equal to N, then the encoder outputs a signal point whose component sum is no greater than N;
On the other hand, if the lining sum is not greater than N, then the encoder can be described as outputting signal points whose component sums are not less than N. ) The encoding scheme described above has at least two important features. First, like any well-designed lattice coding scheme, it provides a so-called “coding gain” and S
/N ratio and, as a result, improve performance. In other words,
The ratio of a) the least squares Euclidean distance between successively transmitted signal points and b) the average power of the transmitted signal points is the "uncoded" system, i.e. the coded with a 2' = 64-element alphabet. It is larger compared to the 6-bit system on leads 12a-d and 13a-b, which can be encoded but are not actually encoded.

More specifically, the 64-element alphabet used in the uncoded case consists of a) 16 4-tuples where each component is +1 or -1, and b) 3 tuples where each component is +1 or -1. Ingredients and +3 ingredients and +
Assuming that it consists of 48 4-tuples containing one component of 3 or -3, the coding gain provided by the coding system according to the invention is 3.01 db.

It is also conceivable to achieve even greater coding gain by using a 128-element alpha vent based on the same lattice of the 256-element alphabet of this example. A consideration of the present invention is some reduction in coding efficiency due to the fact that either of two signal points are generated to represent one input word. However, by sacrificing some coding gain,
You can get more than that.

More specifically, since the lining sum described above is guaranteed to have an upper and lower bound, i.e., it cannot exceed 12 and cannot be less than -12.
The output of the encoder spectrum, and hence the spectrum of the line signal applied to the channel, is guaranteed to have a spectral null at dc. In this regard, see, for example, J., U., Justesen), [
Information rate and power spectrum of digital codes (In
formation Rating Poher 5
pectra of DigitalCodeS)],
IEEE Transaction Op-Information Theory, IT-28 (IEEE Trans, I
information Theary, IT-28)
, 1982, Page 457-472, and G, Pierobon, [Codes for zero spectral density at zero frequency.
Zer.

5pectral density at Zero
Frequency)] IEEE
, IT-30), 1984, Page 435-43
See 9. As explained above, providing spectral nulls at dc is an essential requirement in many data transmission applications. The invention therefore opens the possibility of utilizing lattice codes for data transmission applications and thus ensuring coding gains.

In order to understand how encoder 10 implements these, it is first necessary to explain the operation of lining summation circuit 30. The task of this circuit is to ensure that the sum of signal points at the encoder output is positive if the lining sum is currently negative, and negative if the sum is positive. To achieve this, circuit 30
includes a register 36 that holds the current lining sum.

The sign of this sum, in this example, register 3
The sign represented by the sign bit on one of the six output leads 36a is applied to one input of an exclusive OR gate 38. The other input beam 21a of the gate 38
- represents the sign of the component sum of the grid points on d. This input is the sign bit output of adder 33. gate 38
The outputs of the multipliers 37 in the sign inverter circuit 35
extending individually. Depending on the value of this bit, the multiplier 37
each busses a corresponding one of the grid point components on leads 21a-d to P/S converter 40 unmodified or inverts the sign of that component.

In operation, therefore, if the lining sum and the component sum of the signal point currently output by generator 20 are both positive or both negative, the output of gate 38 will be negative and the component sum of that lattice point The signs of all are inverted.

The signal points to be output are therefore leads 21a-d
The other signal point of the same pair in the selected subset rather than the upper grid point.

Thus, the component summation of the resulting signal points on leads 25a-d produced by multiplier 31 in lining summing circuit 30 is then multi-bit multi-bit in accumulator 39.
When combined with the current lining sum provided on lead 32, the lining sum is driven toward zero. This new value is then stored in register 36.

On the other hand, the lining sum is positive (negative), and the lead 21a
If the component sum of the current grid point on -d is negative (positive), the output of gate 38 will be positive. Leads 21a-d
The above component therefore remains unmodified in the inverter circuit 35.
The lining sum is also driven to zero in this case. If the lining sum and/or component sum is zero at any time,
The output of gate 38 is either ``0'' or ``1'' depending on how zero is represented by multiplier 33 and register 36, and thus the two signals of the identified pair are Any one of the points is selected.

(If necessary, a divider 2 circuit (not shown) can be inserted between the multiplier 31 and the accumulator 39.

This has no effect on the value of the sign bit on field 37, but has the effect of simplifying the implementation of accumulator 39 and register 36 slightly, since the data word being processed is one bit smaller. . ) To understand how signal points greater than zero are implemented, it is necessary to consider again the signaling alpha pair). For example, in Table I, given any initial set of subsets, the individual signal points in the second set of that subset are guided through a particular code pattern change associated with the other subset I. It turns out that you can. Thus, for example, any signal point in subset S2 can be derived from a particular signal point in subset S1 by changing the sign of the last two components. Therefore, the signal point generator 20 includes a) RO
storing in M17 the signal points of a particular one of the subsets, e.g., subset S1; b) reading a particular one of these 32 stored signal points from ROM 17; and C) deriving the output signal points. The lattice encoder 15 is configured to generate a code pattern variation corresponding to the subset to be encoded.

However, signal point generator 20 can be further simplified from the fact that only one signal point of each signal point pair within each subset needs to be generated on leads 21a-d. This can be understood by the following explanation.

For example, the lining sum is the current pressure, and the lead 21a
Assume that the lattice point on -d is the point (-1, 1, 1, 1) (from subset S3). Since the sum of the components of this lattice point is also positive, circuit 30 instructs multiplier 37 to invert the sign of all components of lattice point (-1, 1, 1, 1), and as a result, lead 25a The other signal point of the same pair, ie, signal point (1, -1, -1, -1), is generated on -d. On the other hand, when the lattice point on leads 21a-d is point (1, -1, -1, -1), the circuit 30 has a negative sum of (1, -1, -1, -1) components. Therefore, the multiplier 37 is not instructed to invert. Therefore, in this case as well, points (1, -1, -1, -1) are added to the P/S converter 40.

As a result of the above, ROM 17 only needs to store one of each pair of signal points in the subset, and lattice encoder 15 stores one code bit pattern for three of the four components output by ROM 17. All you need to do is provide. For example, in this exemplary embodiment, only half of Sl, designated as S+ by the table, is stored in ROM 17, and lattice encoder 15 uses the sign bits for leads 13b-d according to table 1 below. generate.

Table■ s　　　　　　　　oo.

S, 101 S　a　　　　　　110 S, 001 s, oi.

S? 100 s, 111 Here, "1" means "change of sign bit", and "0" means "change of sign bit".
” means “do not change the sign bit”.RO
The actual modification of the sign bit of the component on the M output Lee Read B ba is performed by multiplier set 19 . Multiplier set 19 is responsive to the three outputs of lattice encoder 15 on leads 16a-c to add the corresponding one sign bit of the component on second, third and fourth ROM output leads IBb-a. It may or may not change according to the encoder output value.

The particular lattice code used to determine which subset of signal points to output is represented by the lattice diagram shown in FIG. encoder is 0
It has eight "states" named 00.100.010.110.00, 10, 011 and 111. The state of the lattice encoder is the state of at least one received before the current input word.
is determined as a function of at least one bit of an input word. More specifically, in this implementation, the state of the encoder is a) the two bits added to the encoder before the two current bits, and b) the bits added to the encoder before this one. determined as a function. So, for example, if the encoder is in state 001, this means that the previous two bits added to the encoder were "1" and "O" (state bits are read from right to left), and the previous one of the bits of the pair added to the encoder - for example, lead 1
The bit above 3b means "0". Further, if the current bit pair on leads 13a-b is, for example, 11, then the next state is 11.

The two vertical lines of points in FIG. 2 represent the eight possible encoder states in a series of time intervals, and the lines connecting various pairs of states indicate possible state transitions. Thus, for example, the encoder can transition from state so 10 to state 001, but not to state 100.

Each of these connecting lines has a label indicating from which subset the next signal point to be generated will come. In the example above, assume that the current state of the encoder is 001 and that when the next set of bits is output from S/P converter 11, the bit pair on lead 13a-1 will be "11". .

This means that the next signal point to be generated will come from subset S7 since the line connecting state 001 in the left column to state 111 in the right column is labeled S7.

A circuit implementation of lattice encoder 15 is shown in FIG. The two current bits added to the encoder are leads 13a-
Added from b. The two bits previously added to the encoder are held in one bit delay elements 151 and 152. The bit previously applied to the encoder via lead 13b is held in a 1-bit delay element 153, while element 15
3 receives this input from delay element 152. These 3
The value held in one delay element is added to the binary adder 154.15 along with the value of the two current bits on 13a-b.
5 and 156. Each binary adder is ``0'' when its even (odd) input bit has the value ``1''.
Outputs (“1”).

The outputs of adders 154, 155 and 156 are given the appropriate sign bits specified by the lattice of FIG.
Configure a pattern.

The receiver of FIG. 4 is of conventional design. More specifically,
The baseband pulse stream on the channel is applied to an A/D converter 71 and from there to a conventional equalizer 72. Equalizer 72 corrects for distortion in the channel and provides a signal representative of the transmitted data bit stream on its output door 3.

The bits on lead 73 are converted to a multi-bit word by S/P converter 74. More specifically, S/P converter 47 provides one multi-bit signal representing the corresponding one value of the four components of the signal points received on each of its multi-bit output cards 5a-d. . Typically, these component values are not perfectly integer as they were when they were transmitted, due to myriad channel effects, disturbances, etc. that equalizer 72 was unable to correct for. Therefore, typically, for example, (-1, 1, 3, 4,
-2, 8, 1, 0) are received.

A Viterbi decoder 76 receiving the signal points on the boards 5a-d determines what sequence the transmitted signal points actually had.
This is the task. Like the rest of the receiver, the Viterbi decoder has a conventional design and does not require a detailed explanation. Viterht
For details of the operation of the decoder, see, for example, A. J. Viterbi and J.

Written by J. K. Omura (J. K. Omura);
s of Digital Communication
McGraiy-Hill, New York, 1
See 979 publication. Here, decoder 76 is used to determine what was the most likely sequence of signal points transmitted to the grid of FIG. We only mention that we add the so-called Viterbi algorithm to determine the state of . The estimated sequence of signal points is provided on multi-bit output card doors 7a-b. In addition, having knowledge of the sequence of encoder states, the decoder 76 uses leads 13a-b at the transmitter at the time each of those signal points were generated on leads 77a-b.
It becomes possible to output the values of the two bits appearing in "b".

The four bits that appeared on leads 12a-d at that time are recovered from the signal points on leads 77a-d. As stated above, “0” on leads 12a-d
Each of the 16 possible combinations of and "1" results in the same pattern of component scale.

These four bits therefore convert all of the components of the signal points on leads 77a-d to positive values in transcoder 81 and then the corresponding "0" and "
The resulting 6-bit word bits on leads 83a-d and 78a-d are converted to serial format by P/S converter 85 and applied to data sink 90. .

The above description is based on the zero frequency (zero frequency) in principle.
ncy), that is, the spectrum null (spe
Although the focus has been on providing spectral nulls at other frequencies, the principles of the present invention can also be used to provide spectral nulls at other frequencies. For example, dc and 1
It is also possible to simultaneously generate a spectral null at /2T. Here, T is the so-called signaling interval (sig
naling 1nterval 9 and 1
/T is therefore the symbol or po velocity. One way to accomplish this is to split the binary bitstream into two, generate a code in which each bitstream uses the principles of the invention independently, and then incremate the signal points thus generated. (insert) method. In this regard, see, for example, the article by J. Pierce [Some Practical Aspects of Digital Transmission].
tical Aspects of DigitalT
transmission), IEEE Spectrum (
113EIES Spectrum), Vol, 5.1
968, page 63-70.

Alternatively, the spectral nulls at dC and 1/2T can be used to divide each ROM input word into a group of four signal points in each subset rather than just two, as in the exemplary embodiment of the present invention. This can also be achieved by relating.

After transmission of M signal points, a particular one of the four signal points from the identified group is to be generated.
is identified using the following two lining values:

R,=de°, R1 is of course - the same lining sum as used in the example embodiment, and R2 is derived from the sum of the first and third components of the individual transmitted signal points. This is the sum of the second and fourth components.

The points of the individual subsets are within four of these groups, such that one point of the group has both lining values more positive, e.g., point (3, -1, 3, -
3); one point in the group makes both lining values more negative, e.g. point (-3,1, -3,1)
; one point in the group makes one lining value more positive and the other more negative, e.g. point (−
1, 3, -1, 3); and one point in the group makes one lining value more negative and the other more positive, e.g. point (1, -3, 1, -3); Arranged. (For this purpose, points that do not change a particular one of the lining values are considered to make it more positive or more negative than that lining value.) The particular point chosen is therefore one of the four. This is the point where both lining values of are driven towards zero. If a particular one of the lining values is already zero, then
The selection of a signal point can be determined only in relation to the other lining value, and if both are zero, the point is chosen arbitrarily.

This method provides a spectrum that rises more slowly from the spectral null compared to the first interleaving method. This is one of the properties required in many applications.

A further generalization of this approach using large groups of signal points and corresponding numbers of lining values can be employed to provide spectral nulls at other desired rational divisions of the signal frequency. It is possible.

The above description merely illustrates the principles of the invention. For example, although a particular alphabet and a particular lattice code were used in this exemplary embodiment, it will be appreciated that the present invention can be implemented within a system using any of a number of different possible alpha vent and lattice codes. It is.

Further, although the systems disclosed herein may be embodied in the form of a variety of discrete electronic building blocks and components, the present invention contemplates any one or more functions of these building blocks and components, or even all of these functions. However, it could equally well be implemented in a system, for example implemented by one or more suitably programmed processors.

Therefore, it will be apparent to those skilled in the art that various other configurations not expressly or disclosed herein that incorporate the present invention may be devised without departing from the scope and spirit of the present invention.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a transmitter embodying the principle of 2008; Figure 2 illustrates the grid code used in the transmitter of Figure 1; Figure 3 is a block diagram of the transmitter used in the transmitter of Figure 1. and FIG. 4 is a block diagram of a receiver used to recover the data encoded and transmitted by the transmitter of FIG. <Explanation of codes of main parts> Data source...9 Encoder...10

Claims (1)

Claims: 1. In a data transmission system used to generate a sequence of output signals in response to a sequence of (k+n)-bit input words, each of the output signals having a predetermined alphabet of signal points. of the alphabet in response to the n-bit value of each input word in the input word sequence and the value of at least one bit of one preceding input word in the input word sequence. means for identifying one of two predetermined subsets (e.g.
15), where m is an integer greater than n, means for identifying a plurality of signal points of the one subset in response to other k bits of the respective input word (e.g., 17, 19), and a selected one of said plurality of signal points as an independent one of said sequence of output signals;
means (e.g., 30, 35) for generating a signal representing two points, the one point of the signal point being a function of the components of the signal point represented by a previously generated one of the output signal; A system characterized by being selected as. 2. In the system according to claim 1,
A system characterized in that said one of said signal points is selected in response to a lining summation of components of signal points represented by a previously generated one of said output signal. 3. In the system according to claim 2,
Each of the plurality of signal points is a pair of signal points, the sum of the components of one of the signal points of the pair is at least equal to a predetermined value, and the sum of the components of the other signal point of the pair is equal to the sum of the components of the other signal point of the pair. is less than or equal to a predetermined value, and the generating means selects the one of the signal points of the pair when the lining sum is less than the predetermined value, and selects the one of the signal points of the pair when the lining sum is greater than the predetermined value. A system for selecting the other point of the signal point. 4. In the system according to claim 3,
A system characterized in that each of the components of the signal points of the alphabet is an odd integer. 5. In the system according to claim 3,
A system characterized in that the predetermined value is zero. 6. In the system according to claim 3,
A system characterized in that each of the components of the one of the signal points of the pair has the same and opposite magnitude as the corresponding component of the other of the signal points of the pair. 7. A method used in a data transmission system to generate a sequence of signal points, each representing a corresponding input word of a sequence of (k+n)-bit input words, in which each signal point is 2^( ^k^+^m
^+^1^) signal points are selected from a predetermined alphabet of signal points, k, m, and n are predetermined integers, m is greater than n, and the method identifying one of the 2^m predetermined subsets of the alphabet for each input word of the input word sequence in response to the value of at least one bit of one preceding input word in the input word sequence; identifying signal points of a pair of said one subset in response to other k bits of said individual input word, and said pair in response to a value of a component of a previous signal point in said sequence of signal points. A method comprising: generating a selected one of the signal points of the signal point. 8. The method of claim 7, wherein in the generating step, the selected one of the pair of signal points is generated in response to a lining summation of the values of the components of the previous signal point. A method characterized by: 9. The method according to claim 8, wherein the sum of the components of one of the signal points of the pair is at least equal to a certain predetermined value, and the sum of the components of the other signal point of the pair is at least equal to a certain predetermined value. is less than or equal to a predetermined value, and in the generation step, when the lining sum is smaller than the predetermined value, one of the signal points of the pair is generated, and when the lining sum is greater than the predetermined value, the pair is generated. A method characterized in that the other point of the signal point of is generated. 10. A method as claimed in claim 9, characterized in that the individual components of each of the signal points of the alphabet are odd integers. 11. The method of claim 9, wherein the predetermined value is zero. 12. A method as claimed in claim 9, in which each subset of the alphabet includes a particular one of the signal points of the alphabet and each of its components corresponds to a particular one of the signal points of the alphabet. A method characterized in that the signal is divided to include signal points that are negative of the component.