EP0166560B1

EP0166560B1 - Multi-dimensional coding for error reduction

Info

Publication number: EP0166560B1
Application number: EP85304296A
Authority: EP
Inventors: Arthur Robert Calderbank; Neil James Alexander Sloane
Original assignee: American Telephone and Telegraph Co Inc; AT&T Corp
Current assignee: AT&T Corp
Priority date: 1984-06-25
Filing date: 1985-06-17
Publication date: 1991-04-03
Also published as: JP2677348B2; US4581601A; CA1289667C; EP0166560A2; EP0166560A3; DE3582369D1; JPS6113821A

Description

Technical Field

This invention relates to coding information so as to reduce errors caused by transmission from being included in the received signal and, in particular, to multi-dimensional coding.

Background of the Invention

When information is sent from a transmitter over a-channel to a receiver, the information signals are often distorted by noise and other causes. Sometimes the information signals are distorted to such an extent that the received signals do not duplicate the information sent.
In order to reduce errors in the received signals, the information is coded at the transmitter. There are two basic coding schemes: block coding and convolution coding. These coding schemes are explained in detail in a book entitled "Error Control Coding: Fundamentals and Applications" by S. Lin et al.
Simply stated, block coding introduces n-k redundant bits to a block of k bits of information to derive a coded block of n bits which is transmitted to a receiver. For binary signals, there are 2^kcode words, each of length n, and the set is called an (n, k) block code. Convolutional coding introduces m bits from previous blocks of information, each having k bits, to derive a coded signal having n bits. The encoder is said to have a memory order of m. The set of codes is called an (n, k, m) convolutional code. The code rate is k/n.
U. S. Patent No. 4,077,021 teaches a technique called set partitioning that assigns signal points to successive blocks of input data. More particularly, a code rate of 4 bits/2-dimensional symbol is shown. Also, a coding gain of 4 db over standard uncoded transmission is obtained. That is, noise immunity is obtained without increasing the power required for transmission. As will be described fully in the detailed description of the present invention, it is desirable to obtain a more efficient coding scheme.
A paper by A. Gersho and V.B. Lawrence in IEEE International Conference on Communications, Amsterdam, 14th-17th May 1984, vol. 1, pages 377-380, entitled "Multi-dimensional Signal Design for Digital Transmission over Bandlimited Channels" discloses a coding arrangement in which each word (of, say, eight bits) is divided into three groups of bits of variable length. The first group, which may contain from 2 to 4 bits, determines the numbers of bits in the other groups. The first and second groups together address an unsigned four-dimensional code-word and the third group determines the signs of the non-zero components of the code-word. This paper also discloses that a ROM table look-up can be used to assign a code-word to each word.
IBM Technical Disclosure Bulletin, vol. 26, no. 2, July 1983, pages 662-664 discloses a coding scheme in which a 6-bit word is divided into two groups, containing four and two bits respectively. The two bits in the second group are expanded to three bits by an eight-state convolutional code (i.e. a convolutional code using three bits of memory). The three bits of the expanded second group are used to specify one of eight subsets into which a two-dimensional constellation of 128 points is divided, and the four bits of the first group are used to determine which point within the specified subset is used.

Summary of the Invention

The invention as claimed in claims 1 and 4 provides a coding apparatus and method respectively which 1) reduces the power consumed, 2) achieves a high code rate, and 3) achieves efficiency in terms of low power use and low error in the received signal.
More particularly, according to one embodiment of the present invention, an information block comprising eight bits of input to the coder is converted into any one of five hundred and twelve four-dimensional code words. The eight bits are changed into an output having nine bits by retaining two input bits from the immediately preceding block and one input bit from two preceding blocks. The output is divided into two signal groups: a first group comprises five bits and a second comprises four bits.
The first group having five uncoded bits, addresses any one of thirty-two (2⁵ = 32) locations of a read only memory. Each location has a code word comprising four numbers, representing the coordinates of a point in four-dimensional space. The numbers appearing in the thirty-two code words include 1, -1, 3, -3, 5 and -5. These code words are shown in tables 1 and 2, included in the detailed description of the invention hereinbelow.
The second group of four bits makes up a vector which determines the sign of the four-dimensional code word read from the read only memory. This scheme is equivalent to having the code word read from any page of a code book having sixteen (2⁴ = ₁₆) pages, each page having thirty-two code words entered therein.
Thus, there is disclosed a trellis code with rate of eight bits per four-dimensional symbol with a gain of 4.7 decibels over standard uncoded transmission. This 0.7 decibel increase over the aforesaid prior art code systems corresponds to improving the block error rate by a factor of 10. The signal constellation comprises five hundred twelve four-dimensional signal points, that is, each symbol has a set of four numbers which defines a signal point in four-dimensional space.
By way of comparison, first, transmission of two consecutive two-dimensional signals using one of the prior art codes with rate four bits per two-dimensional symbol would require the equivalent of 1, 024 because 32² = 1024 ) four-dimensional signal points. That is, the size of the code is reduced. Second, the restriction of the five hundred twelve point constellation to the first two coordinates, or to the last two coordinates, requires only a set of thirty-two signal points. This code rate of eight bits per four-dimensional symbol is suggested for data transmission rates of 9.6 kbits/sec.
In another embodiment of the present invention, a trellis code with rate twelve bits per four-dimensional symbol provides a gain of 4.9 db over standard uncoded transmission. This method is suggested for data transmission rates of 14.4 kbits/sec.
In the limit, when the number, k, of bits in a block approaches infinity, the coding gain is asymptotic to 4.9715 decibels. That is, the difference between the limiting gain and that provided with k = 12 is very small.

Brief Description of the Drawing

FIG. 1 is a prior art system for transmission of encoded signals;
FIG. 2 illustrates the concept of convolutional encoders;
FIG. 3 shows possible transitions of states between two instants in time;
FIG. 4 illustrates error events and the term Euclidean distance;
FIG. 5 shows a convolutional encoder of memory order three;
FIG. 6 shows a signal constellation for uncoded transmission at the rate four bits per two dimensional symbol;
FIG. 7 shows a convolutional encoder embodying the present invention;
FIG. 8 shows a rectangular constellation for uncoded transmission at six bits per two dimensional symbol; and
FIG. 9 shows a signal constellation for trellis codes at the rate four bits per two dimensional symbol.

Detailed Description

Referring to FIG. 1, there is shown a prior art system comprising a digital source 10 supplying a signal to encoder 12. The coded signal from encoder 12 is modulated by device 14 for transmission to a distant location where the signal is demodulated at device 18. The demodulated signal is thereafter decoded at device 20 and sent on to a digital sink 22. The use of encoder 12 reduces the errors caused by noise in the transmission facility 16. The present invention relates to an improvement in the aforesaid encoder 12.
It is necessary to disclose the theoretical basis for the present invention in order to fully appreciate it. Assume that an input block of k bits from a serial bit stream is first converted by a series-to-parallel converter such as device 70 in FIG. 7, such converters being well known, to an input of k parallel bits {aⁱ ₁ 1, {aⁱ ₂ }, {aⁱ ₃ }, ..., {aⁱ _K} prior to

entering the encoder at time i. Assume further that the output of the encoder, at time i, is x' and depends not only on the present value of the input sequence but also on the previous v_i≧0 bits as illustrated in FIG. 2. That is, the encoder is a convolutional encoder as well as a block encoder. If v_j = 0 then {a is said to be a sequence of uncoded bits. The constraint length v is given by
The output x' of the encoder is a fixed function x of the (v + k) variables
That is,
The
is the state of the encoder and there are 2^v states.

Referring to FIG. 3, there is shown a state transition diagram from time i to time (i + 1) for a trellis code with k = 3, v₁ = 0, v₂ = 1, and v₃ = 2. Looking briefly ahead to FIG. 5, there is shown a coder, which is an application of FIG. 2, where the aⁱ ₁ sequence has no memory, that is, v₁ = 0, or uncoded; where a¹ ₂ sequence has one bit of memory, that is, v₂ = 1; and, where the aⁱ ₃ sequence has two bits of memory, that is, v₃ = 2. Because three bits of memory exist, there are (2³ = 8) eight states for the coder. The three bits shown at time i are the bits stored for a₂ at time (i-1), that is, aⁱ ₂ ^-1; for a3 at time (i-1), that is, aⁱ ₃ ^-1; and a3 at time (i-2), that is, a3 ^-2. An edge joins two states at time i and i + 1. Each edge is double in this case, as will be explained below, but only shown drawn singly to simplify the drawing.
The state transition diagram can be understood by examining, for example, the transition from the state '010' at time i to a state at time i + 1. Remembering that at time i the 1 in state '010' is a3 ^-1, at time i + 1 this i the 1 in state '010' is aⁱ ₃ ^-1, at time i + 1 this bit 1 will now be a3 -2 and can be any one of the four codes which end in a 1 : 001, 101, 011, or 111 depending on the next value of aⁱ ₂ ^-1 and aⁱ ₃ -aⁱ ₃ ^-1.
Returning to the theoretical basis, noise in the transmission channel distorts the sequence of signals from the output of the coder:
Then, the signal received say at decoder 20 of FIG. 1, is:
where r^ij = x^ij + z^ij, the z^ij being the noise component. The noise samples z^ij are independent zero-mean Gaussian variables of variance, σ².
The Viterbi algorithm, disclosed at 61 Proceedings of the IEEE 268-278 (No. 3, March 1973), is used to find the most likely path through the trellis given the observed sequence ∥rⁱ∥. The path chosen will not always coincide with the correct path, but will occasionally diverge from it and remerge at a later time. This is called an error event.
An error event E of length 1 lasts from j to (j+I), the sequence ^j, ..., ^(j+l-1) instead of the correct sequence xⁱ, ... , x^(j+l-1). The squared Euclidean distance d², that is, d²(E), between the two paths of E is given by
where
denotes the usual Euclidean norm.
Referring to FIG. 4, there is shown an error event for which the squared Euclidean distance is
The average transmitted power is given by
For small noise variance a², the minimum distance d_min over all error events determines the probability of error. The figure of merit for a trellis code is the normalized minimum distance stated by the ratio:
The bigger this ratio, the better the code. The performance of a coding scheme is measured against that of uncoded transmission at the same rate. The coding gain in decibels, db, is given by the expression:
Basic to the trellis codes of the embodiment disclosed hereinbelow is a rate 3/4 binary convolutional code with a total memory 3 and free distance 4. A portion of the encoder is shown in FIG. 5 which has been disclosed in the aforesaid Lin book at page 292. The three parallel input sequences aⁱ ₁, aⁱ ₂ and a3 determine the output sequence v = (vⁱ ₁ , vⁱ ₂, vⁱ ₃, vⁱ ₄) according to the rules:

and
The
describe the state of the encoder. The possible transitions between states of such an encoder is shown hereinabove in FIG. 3. The edge joining state aⁱ ₂ ^-1 aⁱ ₃ ^-1 a3 ^-2 to state aⁱ ₂ a3 a^i-1 ₃ can be labelled with the outputs:Vⁱ = (vⁱ ₁,vⁱ ₂,vⁱ ₃vⁱ ₄) and ⁱ = (ⁱ ₁, ⁱ ₂, ⁱ ₃, ⁱ ₄) corresponding to this transition so that

and
The binary notation 0,1 is then changed to 1, -1, respectively. An edge joining two states is then labelled with a pair of vectors ( w₁, w2, w₃, l w₄) and ( -w₁, -w₂, -_W3, -w₄ ) where w = ±1 and i = 1, 2, 3, and 4. This defines a trellis encoder with rate 3 bits/ 4-dimensional symbol. The minimum squared distance of this trellis code is simply four times the free distance of the original binary convolutional code, namely 16. This is so because 0 opposite 1 contributes 1 to the free distance while 1 opposite -1 contributes 4 to the squared minimum distance.
Thus far, a trellis code at the low rate 3 bits/4-dimensional symbol was disclosed. Transmission at higher rates, say 8 bits/4-dimensional symbol or 12 bits/4-dimensional symbol requires more channel symbols. Indeed, as is readily apparent from the disclosure thus far, in order to achieve any coding gain, more symbols are needed than for uncoded transmission at the same rate.
Referring to FIG. 6, there is shown a rectangular constellation comprising sixteen ( 2⁴ = 16) signal points for standard uncoded transmission, of binary input, at the rate of 4 bits/ 2-dimensional symbol. For uncoded transmission of a 4-dimensional symbol, two copies of the constellation shown in FIG. 6 are needed, yielding 256 ( 16 x 16 = 256 ) possible signals. Using the formula developed earlier herein, the average power or energy is
that is, 20. Because the minimum squared distance between distinct signals is four, the figure of merit is given by the formula:
For coded transmission, however, 512 signal points are used, namely, twice the signal constellation for uncoded transmission of 4-dimensional symbols. This is so because a block of eight input bits is converted to nine bits using three bits from prior blocks and 2⁹ is 512. This conversion will become clear by referring to FIG. 7, wherein is shown a stream of binary bits on lead 71 converted from serial to parallel in converter 70 and then sent on via two sets of leads 73 and 51.
The first set of leads 73 carries five uncoded bits which are converted from binary form by changing a 0 to a 1 and a 1 to a -1 in a binary converter 72 and then sent on via leads 75 to address any one of thirty-two ( 2⁵ = 32 ) code words, representing signal points, from a storage device such as read only memory ( ROM ) 74. Because each code word defines a point in four dimensional space, four numbers are required for each code word. The numbers of the addressed code word are passed via leads 77 to multipliers 82 ... 88. Representative signal points are shown in Table 1 hereinbelow.
The first column of Table 1 shows the code words representative of signal points in four dimensional space. The number of permutations for each representative code word is shown in column three, giving a total of thirty-two code words stored in ROM 74. The list of thirty-two code words is obtained by permuting the coordinates of the code words in column one.
The second set of leads 51 from serial to parallel converter 70 carries three of the binary input bits to a device 50 which stores three bits from prior blocks as disclosed in detail earlier herein with reference to FIG. 5, and delivers four bits on leads 53 to a device 80. At device 80 the binary bit 0 is converted to 1 and a binary 1 is converted to a -1. The vector W of four bits W_i, W₂, W_s, and W₄ are then delivered to multipliers 82 ... 88. The amber y₁ of the accessed code word is then multiplied by W₁ from lead 81 at multiplier 82 to generate output x_i. Likewise, x₂, x_s, and x₄ are generated and sent over leads 89.
Because there are four bits W₁ , W₂, W₃, and W₄, and because there are two values 1 or -1 for each, together there can be sixteen (2⁴ = 16 ) different permutations of these bits. Because there are thirty-two signal points ( x₁ x₂ , x₃ x₄) in the set S(w) which satisfy the requirement x_i = w_i (mod 4), for i = 1, 2, 3, and 4, there are 512 ( 16 x 32 = 512 ) symbols in the signal constellation, because all permutations are allowed. Thus, the coding scheme of the present invention can be thought of as a code book comprising sixteen pages with thirty-two code words on each page. Each page corresponds to the vector W_i, where i = 1, 2, 3, and 4. The thirty-two code words correspond to the entries in ROM 74. The entire list of thirty-two code words in ROM 74 is shown in Table 2 hereinbelow.
The set of coordinates (x₁, x₂, x₃, x₄) representing the input block of 8 bits on leads 89 is then sent on to a modulator. The present invention relates to an encoder only and therefore other equipment cooperating with the encoder is not disclosed in any detail, beyond what was disclosed earlier with reference to FIG. 1.
The distance d( A, B ) between two sets of vectors A and B is given by the expression:
The partition into sets S( w ) satifies the following metric properties:

(M1): if x, y ∈ S( w ), then ∥x-y∥²≧ 16; and
(M2): if v ≠ w, then d²(S(v), S(w)) = ∥ v-w ∥².

_i

₂

₃

₄

₁

₂

₃

₄

_i

₂

₃

₄

₁

₂

₃

₄

_i

²

Earlier hereinabove, a trellis code with rate 3 bits/4-dimensional symbol having a minimum squared distance d² _m in = 16 was disclosed. In order to achieve a higher transmission rate of 8 bits/4-dimensional symbol, five uncoded bits were added, obtaining an input of eight parallel sequences to the encoder in FIG. 7:

{aⁱ ₁ }, {aⁱ ₂ }, {a3 },..., {aⁱ ₈ }. The sequences {aⁱ ₂ } {aⁱ ₃ } determine the state a ⁱ ₂ ^-1 aⁱ ₃ ^-1 aⁱ ₃ -2 of the encoder in FIG. 7. An edge joining two states can now be labelled by the sixty-four vectors in the set S(v) U S (-v). This is so because there are sixty-four parallel transitions between states
aⁱ ₂ ^-1 aⁱ ₃ ^-1 aⁱ ₃ -2 and a2 aⁱ ₃ aⁱ ₃ ^-1 corresponding to the sixty-four possible inputs aⁱ ₄ ... aⁱ ₈. Furthermore, any fixed assignment of code symbol in S(v) U S(-v) to inputs a) aⁱ ₄... aⁱ ₈ is permitted.

The properties (M1) and (M2) guarantee that the squared distance of any error event is at least 16. Consider any error event in the eight state trellis of length 1. If the squared distance for the low-rate code is
then the squared distance for the high rate code is at least
The property (M2) implies that the minimum squared distance of the high-rate code is at least 16. The average signal power P of the 512 point signal constellation is given by the expression:
Referring to FIG. 8, there is shown a signal constellation comprising sixty-four signal points which is used for standard uncoded transmission at the rate of 6 bits/2-dimensional symbol. To transmit a 4- dimensional symbol at a rate of 12 bits/symbol, a constellation comprising two such copies are needed. The number of possible signals will be 4,096 ( 64 x 64 = 4096 ). The average signal power
Thus,
For coded transmission using three bits from prior blocks, 8,192 ( 2¹³ = 8192 ) signal points are needed. As in the 8 bits/4-dimensional symbol, the signal constellation is partitioned into sixteen sets S(w) according to congruence of the entries modulo 4. Each set S(w) will contain, however, 512 signal points, or code words. Representative signal points are listed hereinbelow in Table 3.
In order to obtain a transmission rate of 12 bits/4-dimensional symbol it is necessary to add nine uncoded bits to the four derived bits from FIG. 5, to obtain a total of 13. There are now 1024 parallel transitions between states aⁱ ₂ -1 aⁱ ₃ ^-1 aⁱ ₃ -2 and

a2 a3 a3 ^-1 in the eight state trellis.

If the edge corresponding to this transition was originally labelled ± w, it is now labelled with the 1024 vectors in S(w) U S(-w). The metric properties (M1) and (M2) guarantee that the squared minimum distance of the high-rate code is equal to the squared minimum distance of the low-rate code, which is 16. The average signal power is 108.625, and so the figure of merit is:
and the coding gain is:
Summarizing the aforesaid disclosure, in order to achieve coded transmission at a rate of k bits per four dimensional signal, (k-3) uncoded bits are added to the low rate trellis code, that is, 3 bits per four dimensional symbol, as disclosed hereinabove, with reference to FIG. 3. There are 2(^k-2) parallel transitions between

states aⁱ ₂ ^-1 aⁱ ₃ ^-1 aⁱ ₃ ^-2 and
aⁱ ₂ a3 aⁱ ₃ ^-1 in the eight state trellis.

^3-2

Coded transmission requires 2^(k+1) signal points. The points of the lattice (2Z + 1)⁴, where (2Z + 1) represents the set of odd numbers, lie in shells around the origin consisting of sixteen vectors of energy four, sixty-four vectors of energy twelve, ... , shown summarized in Table 3. The 2^k+1 signal points are obtained by taking all points of energy four, twelve, twenty, ... and just enough points of a final shell to bring the total number up to 2^k+1. The signal constellation is partitioned into sixteen sets S(w) according to congruence of the entries modulo four. Each set contains 2^k-3 signal Points. Thus, when k = 8, each set has thirty-two signal points ( 2^8-3 = 32 ) as is shown in FIG. 9. Edges in the eight state trellis originally labelled + w are now labelled with the 2^k-2 vectors in S(w) U S(-w). The metric properties (M1) and (M2) guarantee that the minimum squared distance of this trellis code is sixteen.
It can be shown that as k increases, that is, in the limiting case, the limiting coding gain is 10 log₁₀π = 4.914 db. That is, the maximum coding gain is 4.914 db. But the coding gain for twelve bits per four dimensional symbol is 4.904 db and the coding gain for eight bits per four dimensional symbol is 4.717 db. Thus, the scheme disclosed by the present invention is an efficient method of coding.

Claims

1. Apparatus for coding k bits of information, k > 4, into a four-dimensional code-word comprising:

serial to parallel means (70) for converting k serial binary bits into k parallel bits, said parallel bits being separated into first and second groups of signals, said first group of signals comprising k-3 bits and said second group of signals comprising 3 bits;

converter means (72) for converting the binary 1 's to -1 's and binary 0's to 1 's of said first group of signals for addressing any one of a plurality of four-dimensional code words, said code words being stored in a memory device (74), said code words consisting of four odd numbers;

a convolutional encoder (50), which comprises memory means for storing three bits,for expanding the number of bits in said second group of signals by one;

converting means (80) for converting the expanded bits from binary 1's to -1's and binary 0's to 1's; and

multiplying means (82, 84, 86, 88) for multiplying the code words from said read only memory by said expanded and converted second group of signals, which determine the sign of the 4 numbers of the four-dimensional code word, to derive an encoded four-dimensional code word for each block of k bits of information.

2. Apparatus as claimed in claim 1 wherein k = 8, said read only memory comprises a set of thirty-two four-dimensional code words, and

said encoded four-dimensional code-word is any one signal of a signal constellation comprising five hundred and twelve four-dimensional code words.

3. Apparatus as claimed in claim 1 wherein k = 12,

said read only memory comprises a set of five hundred and twelve four-dimensional code words, and

said encoded four-dimensional code-word is any one signal of a signal constellation comprising eight thousand, one hundred and ninety-two four-dimensional code words.

4. A method of coding k bits of information, k > 4, into a four-dimensional code-word comprising:

converting k serial binary bits into k parallel bits, said parallel bits being separated into first and second groups of signals, said first group of signals comprising k-3 bits and said second group of signals comprising 3 bits;

converting the binary 1's to -1's and binary 0's to 1's of said first group of signals for addressing any one of a plurality of four-dimensional code words, said code words being stored in a memory device, said code words consisting of four odd numbers;

expanding the number of bits in said second group of signals by one by means of an eight-state convolutional code;

converting the expanded bits from binary 1 's to -1 's and binary 0's to 1 's; and

multiplying the code words from said read only memory by said expanded and converted second group of signals, which determine the sign of the 4 numbers of the four-dimensional code word, to derive an encoded four-dimensional code word for each block of k bits of information.

5. A method as claimed in claim 4 wherein k = 8, said read only memory comprises a set of thirty-two four-dimensional code words, and

6. A method as claimed in claim 4 wherein k = 12,