JPS6395558A - Address converter - Google Patents

Abstract

PURPOSE:To protect a data exchanging memory by dividing this memory according to the information on a position where a CPU board is attached and inhibiting the accesses given from other CPU boards. CONSTITUTION:The higher 4 bits of an address signal of a CPU are inputted to an input terminal 11 of an address decoding circuit 1 and an output terminal 12 is set at '1' when the value of said 4 bis is equal to '8'. An encoding circuit 2 encodes the attaching position of a CPU board and delivers this encoded value to an output terminal 22. A data selecting circuit 3 supplies the higher 4 bits of an address signal of the CPU to an input terminal 31 and the output signal of the circuit 2 to an input terminal 32 respectively. Then the circuit 3 delivers the signal supplied to an input terminal 32 when a selection terminal 34 is equal to '1' and then outputs the signal inputted to the terminal 31 when the terminal 34 is equal to '0'. Thus a data exchanging memory is divided by the slot position of the CPU board. Then it is impossible to give accesses to the same area from plural CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is a system in which memory shared by a plurality of CPU boards is accessed. Although the address space is the same from the software perspective, the actual memory is separated without interfering with each other, so multi-CPU
Effective in the system.

Conventional technology Figure 2 shows multiple Cs sharing memory for data exchange.
FIG. 1 is a configuration diagram of a system including a PU board. In FIG. 2, 4 is a CPU board including a CPU and its peripherals, and there are a plurality of them. 5 is a memory for data exchange d, and access to this memory from the CPU board is 6.
This is done via the system bus.

FIG. 3 shows how the address space for data exchange allocated on the entire address space of the CPU as seen from each CPU board 4 is related to the actual memory for data exchange. Normally, the address of the data exchange memory 5 is allocated to a part of the total address space when viewed from the CPU on the CPU board 4. Therefore, in order to access the memory for data exchange, the CPU must access the address space allocated for data exchange. That is, the CPU on the CPU board 4
An address space for data exchange is allocated on the entire address space of , and when this area (shaded area) is accessed,
It accesses memory for data exchange.

Conventionally, the space allocated for this data exchange was shared by multiple CPU boards, and since the area used was divided by software, protection from other CPUs was left to the software. It had been.

Problems to be Solved by the Invention These conventional circuits have the drawback that protection from other CPUs is not complete and the contents of the memory can be destroyed due to software bugs or the like.

An object of the present invention is to provide a circuit that protects a memory for data exchange with a simple configuration.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention divides the memory for data exchange based on the position information where the CPU board is installed, and prevents it from being accessed by other CPU boards. The purpose is to protect memory for data exchange.

Effects of the present invention With the above-described configuration, the address signal of the CPU when accessing the data exchange memory is converted based on the position information of the slot in which the CPU board is installed, so that the data exchange memory is connected to the slot of the CPU board. It is divided by position, making it impossible for multiple CPUs to access the same area.

Embodiment Hereinafter, an embodiment of the address translation device of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the address translator of the present invention. In FIG. 1, 1 is an address decoding circuit, which has an input terminal 11 and an output terminal 12,
A CPU address bus signal is input to an input terminal 11, and access to an address space for data exchange is detected, and a detection signal is output to an output terminal 12. 2 is an encoding circuit, which has an input terminal 21 and an output terminal 22;
The mounting position of the CPU board is encoded and output to the output terminal 22. 3 is a data selection circuit, which has input terminals 31, 32, an output terminal 33, and i! It has a selection terminal 34, and outputs the signal input to the input terminal 31 or 32 to the output terminal 33 depending on the state of the selection terminal 34.

Here, we will take as an example a system that uses a CPU with a 20-bit address space, sets 64 bytes from addresses 80000 to 8FFFF as address space for data exchange, and accesses memory for data exchange in 64 byte units. explain in detail.

The upper 4 bits of the CPU's address signal are input to the input terminal 11 of the address decoding circuit l, and the value is
’, the output terminal 12 is set to “1”. Encoding circuit 2
encodes the mounting position of the CPU board and outputs the value to the output terminal 22. For example, if the mounting position is "3", 3' is output to the output terminal 22.

The data select circuit 3 inputs the upper 4 bits of the CPU's address signal to an input terminal 31 and the output signal of the encode circuit 2 to an input terminal 32, and when the selection terminal 34 is at 1 degree, the data is input to the input terminal 32. Output the signal and select terminal 3
4 outputs the signal input to the input terminal 31 when it is "O".

That is, for example, when the CPU board installed in slot 3 accesses the data exchange memory, the address signal 3xxxx is converted to 3xxxx, and when the CPU board installed in slot n accesses the data exchange memory, the address signal 3xxxx is converted to 3xxxx. Address signal 8xxxx is converted to nxxxx.

(x is an arbitrary 4-bit value) Therefore, 64 bytes are allocated to each CPU board corresponding to the installed slot position, and each area does not interfere with each other.

Effects of the Invention As described above, according to the present invention, a space for data exchange can be shared between each other and other CPUs with an extremely simple circuit configuration.
It can be taken without interference from U, which is practical and extremely useful.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an address translation device according to an embodiment of the present invention, Fig. 2 is a block diagram of a data exchange device comprising a plurality of CPUs, and Fig. 3 is a block diagram of a conventional address translation device. It is. 1...Address decoding circuit, 2...
Encoding circuit, 3... Data selection circuit,
4... CPU board, 5... Memory for data exchange, 6... System bus, 11...
...Input terminal, 12...Output terminal, 21...
...Input terminal, 22...Output terminal, 31°32...Input terminal, 33...Output terminal, 34...Selection terminal. Figure 2 Figure 3

Claims (1)

[Claims] In a system that allocates space for data exchange on the CPU address space, an encoding circuit detects the mounting position of the CPU board on which the CPU is mounted, and an address decoding circuit detects that the space for data exchange has been accessed. , a part of the CPU address signal and the C
A symbol indicating the mounting position obtained by an encoding circuit that detects the mounting position of the PU board is used as an input signal, and an output signal of an address decoding circuit that detects access to the space for data exchange is used as a selection signal, and output. An address conversion device that includes a data selection circuit that switches signals, and converts a CPU address signal in consideration of the mounting position of a CPU board when an address space for data conversion is accessed.