JPS639218A - Channel selection device - Google Patents
Channel selection deviceInfo
- Publication number
- JPS639218A JPS639218A JP15303186A JP15303186A JPS639218A JP S639218 A JPS639218 A JP S639218A JP 15303186 A JP15303186 A JP 15303186A JP 15303186 A JP15303186 A JP 15303186A JP S639218 A JPS639218 A JP S639218A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- tuning
- point
- frequency
- discrimination
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 claims description 5
- 238000001514 detection method Methods 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 6
- 230000003321 amplification Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 238000013459 approach Methods 0.000 description 1
Landscapes
- Superheterodyne Receivers (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
この発明は、選局チャンネルの所属バンドによらず、常
に最適な同調選局を可能にした選局装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a channel selection device that always enables optimum tuning regardless of the band to which a selected channel belongs.
[従来の技術]
テレビジョン受像機やビデオテープレコーダ等に組み込
まれた選局装置には、選局指令を同調電圧として与える
ボルテージソンセサイザ方式や、位相ロックドループ回
路から得られる正確な周波数にもとづいて選局を行うP
L L周波数シンセサイザ方式などが知られている。[Prior Art] Tuning devices built into television receivers, video tape recorders, etc. use a voltage sensor system that applies tuning commands as a tuning voltage, or a voltage sensor system that applies tuning commands as a tuning voltage, or a system that uses accurate frequency control that is obtained from a phase-locked loop circuit. P to select stations based on
The LL frequency synthesizer method is known.
ボルテージソンセザイザ方式の選局装置は、高速デバイ
スを必要とせず比較的回路構成も簡単であるため、普及
機はほとんどこの方式を採用している。第3図に示す従
来の選局装置1は、この種のボルテージノンセサイザ方
式を用いるものであり、受信アンテナ2に接続された選
局回路3が、選局制御回路4から供給される同調電圧に
応じて希望チャンネルのRF倍信号同調選局するもので
ある。受信アンテナ2から選局回路3内に送られてきた
RF倍信号、高周波増幅回路3aにて増幅され、混合回
路3bにて局部発振回路3cの出力を混合されて、中間
周波とされ、選局回路3に接続された映像中間周波増幅
回路5に供給される。映像中間周波増幅回路5には、周
波数弁別回路6が接続してあり、選周回路3にて同調選
局された信号は、キャリア周波数を中心周波数とするS
字状の弁別特性に従って弁別され、その弁別出力が選局
制御回路4に供給される。Since the voltage sensor type channel selection device does not require high-speed devices and has a relatively simple circuit configuration, most popular machines use this method. The conventional tuning device 1 shown in FIG. The RF multiplied signal tuning of the desired channel is performed according to the voltage. The RF multiplied signal sent from the receiving antenna 2 to the tuning circuit 3 is amplified by the high frequency amplification circuit 3a, mixed with the output of the local oscillation circuit 3c by the mixing circuit 3b, and made into an intermediate frequency, which is then used for tuning. The signal is supplied to a video intermediate frequency amplification circuit 5 connected to the circuit 3. A frequency discrimination circuit 6 is connected to the video intermediate frequency amplification circuit 5, and the signal tuned by the frequency selection circuit 3 is an S
Discrimination is performed according to the character-shaped discrimination characteristic, and the discrimination output is supplied to the channel selection control circuit 4.
[発明が解決しようとする問題点]
上記従来の選局装置1は、選局制御回路4に対して希望
チャンネルを指定すると、選局制御回路4がオートスキ
ャンを開始し、選局に必要な同調電圧を徐々に変化させ
ていく。同調電圧の変化とともに、選局回路3内に局部
発振回路3cの発振周波数が変化し、周波数弁別回路6
の同調点が8字特性の中心周波数に接近する。このとき
、周波数弁別回路6の弁別出力は、中心周波数に対応す
る最適電圧を越えて変化し、一旦S字の極小点を与える
電圧まで至る。このため、従来の選局制御回路4は、8
字の極小点に至った時点で、そのときの同調電圧からあ
らかじめ決めである一定のオフセット電圧を差し引いた
ものを、最適同調電圧として選局回路3に供給していた
。しかし、周波数弁別回路6の弁別特性は、希望チャン
ネルの所属バンドによって8字の形状が異な−)でおり
、このためバンドに関係なく一定のオフセット電圧を差
し引く方法では、最適な同調選局は望めず、チャンネル
によっては同調不良を招く等の問題点があった。[Problems to be Solved by the Invention] In the conventional channel selection device 1 described above, when a desired channel is designated to the channel selection control circuit 4, the channel selection control circuit 4 starts auto-scanning and performs the necessary channel selection. Gradually change the tuning voltage. As the tuning voltage changes, the oscillation frequency of the local oscillation circuit 3c in the tuning circuit 3 changes, and the frequency discrimination circuit 6
The tuning point approaches the center frequency of the figure-8 characteristic. At this time, the discrimination output of the frequency discrimination circuit 6 changes beyond the optimum voltage corresponding to the center frequency, and once reaches the voltage that provides the minimum point of the S-shape. For this reason, the conventional tuning control circuit 4 has 8
When the minimum point of the character is reached, the tuning voltage obtained by subtracting a predetermined fixed offset voltage from the tuning voltage at that time is supplied to the tuning circuit 3 as the optimum tuning voltage. However, the discrimination characteristic of the frequency discrimination circuit 6 is that the shape of the figure 8 is different depending on the band to which the desired channel belongs, and therefore, optimal tuning cannot be expected with the method of subtracting a constant offset voltage regardless of the band. First, there were problems such as poor tuning depending on the channel.
1問題点を解決するだめの手段]
この発明は、上記問題点を解決)−たものであり、外部
から与えられる同調電圧に応じた局部発振周波数により
希望チャンネルの信号を同調選局する選局回路と、この
選局回路が同調選局した信号を周波数弁別する周波数弁
別回路と、この周波数弁別回路の弁別出力の中心周波数
を挟んで点対称位置にある2点を与える同調電圧を検出
し、これらの同調電圧の平均値として前記中心周波数を
与える同調電圧を算出し、算出された同調電圧を前記選
局回路に供給する選局制御手段とから構成したことを特
徴とするものである。[Means for Solving Problem 1] This invention solves the above problems) and provides a tuning method for tuning the signal of a desired channel using a local oscillation frequency according to a tuning voltage applied from the outside. A circuit, a frequency discrimination circuit for frequency discriminating the signal tuned by this tuning circuit, and detecting a tuning voltage that gives two points located at symmetrical positions across the center frequency of the discrimination output of this frequency discrimination circuit, The present invention is characterized by comprising a tuning control means for calculating a tuning voltage giving the center frequency as an average value of these tuning voltages and supplying the calculated tuning voltage to the tuning circuit.
1作用」
この発明は、選局回路が同調選局した信号を周波数弁別
する周波数弁別回路の弁別出力から、S字状弁別特性の
中心周波数を挟んで点対称位置にある2点を与える同調
電圧を検出し、これらの同調電圧の平均値として得られ
る電圧を最適同調電圧として選局回路に供給する。1. This invention provides a tuning voltage that provides two points located point-symmetrically across the center frequency of the S-shaped discrimination characteristic from the discrimination output of a frequency discrimination circuit that discriminates the frequency of a signal tuned by the tuning circuit. is detected, and the voltage obtained as the average value of these tuning voltages is supplied to the tuning circuit as the optimum tuning voltage.
[実施例]
以下、この発明の実施例について、第1.2図を参照し
て説明する。第1図は、この発明の選局装置の一実施例
を示す回路構成図、第2図は、第1図に示した回路各部
の信号波形図である。[Example] Hereinafter, an example of the present invention will be described with reference to FIG. 1.2. FIG. 1 is a circuit configuration diagram showing an embodiment of the channel selection device of the present invention, and FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG.
第1図中、選局装置IIは、選局制御回路12と、この
選局制御回路12と周波数弁別回路6の間に設けたウィ
ンドウ・コンパレータ回路13が、選局制御手段を構成
している。ウィンドウ・コンパレータ回路13は、周波
数弁別回路6の弁別出力について極大点を与える点と極
小点を与える点の2点で検出するものであり、各点にお
ける弁別出力はウィンドウ・コンパレータ回路13を介
して選局制御回路12内に取り込まれる。選局制御回路
12は、上記2点に対応する同調電圧Va。In FIG. 1, the tuning device II includes a tuning control circuit 12 and a window comparator circuit 13 provided between the tuning control circuit 12 and the frequency discrimination circuit 6, which constitute tuning control means. . The window comparator circuit 13 detects the discrimination output of the frequency discrimination circuit 6 at two points: a point giving a maximum point and a point giving a minimum point, and the discrimination output at each point is detected via the window comparator circuit 13. It is taken into the channel selection control circuit 12. The tuning control circuit 12 sets the tuning voltage Va corresponding to the above two points.
V bを記憶する記憶回路12aと、この記憶回路12
aから読み出した同調電圧Va、Vbの平均値を算出す
る演算回路+2bとを内蔵しており、この演算回路+2
bの出力をもって最適同調電圧Vmとする。A memory circuit 12a that stores Vb, and this memory circuit 12
It has a built-in arithmetic circuit +2b that calculates the average value of the tuning voltages Va and Vb read from a, and this arithmetic circuit +2
Let the output of b be the optimum tuning voltage Vm.
従って、いま選局制御回路12が設定された希望チャン
ネルに同調させるため、同調電圧を漸増させていくと、
まず緩やかな同調範囲に入った時点で、映像中間周波増
幅回路5の出力から第2図(A)に示した同期信号が検
出される。そして、同期信号の検出に続いて第2図(B
)に示したように、周波数弁別回路6の弁別出力も増□
加側に振れ、同図(C)に示すごとく、ウィンドウ・コ
ンパレータ回路13の極大点検出出力が得られる。Therefore, if the tuning control circuit 12 gradually increases the tuning voltage in order to tune to the desired channel set,
First, when the tuning range is moderate, the synchronization signal shown in FIG. 2(A) is detected from the output of the video intermediate frequency amplification circuit 5. Then, following the detection of the synchronization signal, Fig. 2 (B
), the discrimination output of the frequency discrimination circuit 6 is also increased □
As a result, the maximum point detection output of the window comparator circuit 13 is obtained as shown in FIG.
次に、同調点がS字特性内に至ると、周波数弁別回路6
の弁別出力は減少に転じ、最適受信点を通り越して極小
点に至る。同調点が極小点に至ったことは、第2図(D
)に示したウィンドウ・コンパレータ回路13の極小点
検出出力により判断される。Next, when the tuning point reaches the S-shaped characteristic, the frequency discrimination circuit 6
The discrimination output begins to decrease, passing the optimal reception point and reaching the minimum point. The fact that the tuning point has reached the minimum point is shown in Figure 2 (D
) is determined based on the minimum point detection output of the window comparator circuit 13.
ここで、ウィンドウ・コンパレータ回路!3の出力のう
ち、極大点検出出力と極小点検出出力との間に形成され
る空白部分の中央の点が、最適受信点となるのであるが
、この空白部分の両端を与える同調電圧Va、Vbは、
ウィンドウ・コンパレータ回路13の極大点検出出力の
立ち下がりと極小点検出出力のぐち上がりに同期して記
憶回路+2aに記憶される。従って、記憶回路12aか
ら同調電圧Va、、Vbを読み出し、これらを演算回路
12 )]にて平均することにより、第2図(E)に示
すごとく、最適同調電圧Vmが得られる。この演算回路
12aから得られた最適同調電圧Vmは、ただちに選局
回路3に供給され、これにより最適の同調選局が行われ
る。Here, the window comparator circuit! Among the outputs of 3, the center point of the blank area formed between the local maximum point detection output and the local minimum point detection output is the optimal reception point, and the tuning voltage Va that gives both ends of this blank area, Vb is
The signal is stored in the storage circuit +2a in synchronization with the fall of the maximum point detection output of the window comparator circuit 13 and the rise of the minimum point detection output. Therefore, by reading out the tuning voltages Va, . The optimal tuning voltage Vm obtained from the arithmetic circuit 12a is immediately supplied to the tuning circuit 3, thereby performing optimal tuning.
このように、に記選局装置11は、選局回路3が同調選
局した信号を周波数弁別する周波数弁別回路6の弁別出
力から、S字状弁別特性の中心周波数を挟んで点対称位
置にある2点(極大点と極小点)を与える同調電圧Va
、Vbを検出し、これらの同調電圧Vaと■bの平均値
として得られる電圧Vmを最適同調電圧として選局回路
3に供給する構成としたから、希望チャンネルの所属バ
ンドによって周波数弁別回路6の弁別特性のS字形状が
変わろうとも、常に周波数弁別回路6の弁別特性のS字
の中央で最適受信点を設定することができ、あらかじめ
決めておいたオフセット電圧を極小点を与える電圧から
差し引〈従来の選局装置1と異なり、常に確実に最適受
信状態を実現することができる。In this way, the station selection device 11 is located at a point symmetrical position across the center frequency of the S-shaped discrimination characteristic from the discrimination output of the frequency discrimination circuit 6 that discriminates the frequency of the signal tuned by the channel selection circuit 3. Tuning voltage Va that gives two points (maximum point and minimum point)
, Vb are detected, and the voltage Vm obtained as the average value of these tuning voltages Va and ■b is supplied to the tuning circuit 3 as the optimum tuning voltage. Even if the S-shape of the discrimination characteristic changes, the optimum reception point can always be set at the center of the S-shape of the discrimination characteristic of the frequency discrimination circuit 6, and the predetermined offset voltage can be inserted from the voltage that gives the minimum point. <Unlike the conventional channel selection device 1, it is possible to always achieve the optimum reception state.
[発明の効果]
以上説明したように、この発明は、選局回路が同調選局
した信号を周波数弁別する周波数弁別回路の弁別出力か
ら、S字状弁別特性の中心周波数を挟んで点対称位置に
ある2点を与える同調電圧を検出し、これらの同調電圧
の平均値として得られる電圧を最適同調電圧として選局
回路に供給する構成としたから、希望チャンネルの所属
バンドによって周波数弁別回路の弁別特性のS字形状か
変わろうとも、常に周波数弁別回路の弁別特性のS字の
中央で最適受信点を設定することができ、あらかじめ決
めておいたオフセット電圧を極小点を与える電圧から差
し引〈従来の選局装置と異なり、常に確実に最適受信状
態を実現することができる等の優れた効果を奏する。[Effects of the Invention] As explained above, the present invention provides point-symmetrical positions across the center frequency of the S-shaped discrimination characteristic from the discrimination output of the frequency discrimination circuit that discriminates the frequency of the signal tuned by the channel selection circuit. The tuning voltage that gives the two points in Even if the S-shape of the characteristic changes, the optimum reception point can always be set at the center of the S-shape of the frequency discrimination circuit's discrimination characteristic, and a predetermined offset voltage can be subtracted from the voltage that gives the minimum point. Unlike conventional channel selection devices, the present invention has excellent effects such as being able to always reliably achieve optimal reception conditions.
第1図は、この発明の選局装置の一実施例を示す回路構
成図、第2図は、第1図に示した回路各部の信号波形図
、第3図は、従来の選局装置の一例を示す回路構成図で
ある。
3190選局回路、6.、、周波数弁別回路。
11.0.選局装置、+2.、、選局制御回路。
13、、、ウィンドウ・コンパレータ回路。FIG. 1 is a circuit configuration diagram showing an embodiment of the channel selection device of the present invention, FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG. 1, and FIG. 3 is a diagram of a conventional channel selection device. FIG. 2 is a circuit configuration diagram showing an example. 3190 channel selection circuit, 6. ,,frequency discrimination circuit. 11.0. Channel selection device, +2. ,,Tuning control circuit. 13. Window comparator circuit.
Claims (1)
より希望チャンネルの信号を同調選局する選局回路と、
この選局回路が同調選局した信号を周波数弁別する周波
数弁別回路と、この周波数弁別回路の弁別出力の中心周
波数を挟んで点対称位置にある2点を与える同調電圧を
検出し、これらの同調電圧の平均値として前記中心周波
数を与える同調電圧を算出し、算出された同調電圧を前
記選局回路に供給する選局制御手段とからなる選局装置
。a tuning circuit that tunes and tunes a signal of a desired channel using a local oscillation frequency according to a tuning voltage applied from the outside;
This tuning circuit detects the frequency discrimination circuit that frequency-discriminates the frequency of the signal tuned by this tuning circuit, and the tuning voltage that gives two points located symmetrically across the center frequency of the discrimination output of this frequency discrimination circuit, and these tuning voltages are detected. A tuning device comprising tuning control means for calculating a tuning voltage giving the center frequency as an average voltage value and supplying the calculated tuning voltage to the tuning circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15303186A JPS639218A (en) | 1986-06-30 | 1986-06-30 | Channel selection device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15303186A JPS639218A (en) | 1986-06-30 | 1986-06-30 | Channel selection device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS639218A true JPS639218A (en) | 1988-01-14 |
JPH0318369B2 JPH0318369B2 (en) | 1991-03-12 |
Family
ID=15553455
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15303186A Granted JPS639218A (en) | 1986-06-30 | 1986-06-30 | Channel selection device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS639218A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0336223U (en) * | 1989-08-16 | 1991-04-09 | ||
JPH0511548U (en) * | 1991-07-25 | 1993-02-12 | 株式会社東芝 | Order wire receiver |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57109415A (en) * | 1980-12-26 | 1982-07-07 | Sony Corp | Voltage control tuning circuit |
-
1986
- 1986-06-30 JP JP15303186A patent/JPS639218A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57109415A (en) * | 1980-12-26 | 1982-07-07 | Sony Corp | Voltage control tuning circuit |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0336223U (en) * | 1989-08-16 | 1991-04-09 | ||
JPH0511548U (en) * | 1991-07-25 | 1993-02-12 | 株式会社東芝 | Order wire receiver |
Also Published As
Publication number | Publication date |
---|---|
JPH0318369B2 (en) | 1991-03-12 |
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