JPS6392034A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6392034A JPS6392034A JP23734686A JP23734686A JPS6392034A JP S6392034 A JPS6392034 A JP S6392034A JP 23734686 A JP23734686 A JP 23734686A JP 23734686 A JP23734686 A JP 23734686A JP S6392034 A JPS6392034 A JP S6392034A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- film carrier
- electrode group
- semiconductor devices
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 239000010931 gold Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910001174 tin-lead alloy Inorganic materials 0.000 claims 1
- 238000004070 electrodeposition Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 241000272161 Charadriiformes Species 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- BQYJATMQXGBDHF-UHFFFAOYSA-N difenoconazole Chemical compound O1C(C)COC1(C=1C(=CC(OC=2C=CC(Cl)=CC=2)=CC=1)Cl)CN1N=CN=C1 BQYJATMQXGBDHF-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、高速なデータ転送ができ、多くの出力トラン
ジスタを有する駆動用半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a driving semiconductor device capable of high-speed data transfer and having many output transistors.
従来の技術
液晶、プラズマそしてＥＬなどのフラットディスプレイ
は、大型化の傾向にあり、大きさ１４インチ程度、ライ
ン数１０００Ｘ１０００本などが要求されている。Conventional flat displays, such as liquid crystal, plasma, and EL, are becoming larger, and are required to have a size of about 14 inches and a number of lines of 1000 x 1000.
データの高速化については、データの多ポート入力化に
より対応されているが、現状では１ポ一トｃｓＭＨｚと
して４ポートで２０ＭＨｚまでしか対応できず、１００
０Ｘ１０００本程度になると６ ｏＭＨｚ程度の転送速
度が要求され現状のままでは対応が難しくなる。Data speeding up has been achieved by inputting data into multiple ports, but currently it is only possible to support up to 20MHz with 4 ports, and 100MHz with 4 ports.
When the number of lines increases to about 0x1000, a transfer rate of about 6 oMHz is required, which becomes difficult to support with the current status.
また、１０００×１ｏｏＯ本程度のディスプレイだなる
と、３２ｃｈの出力トランジスタをもつＩＣが６４個程
必要となシ非常に多くのＩＣを実装する必要がでてくる
。物理的には、出力トランジスタの数を増す事ができる
が、ピン数が多くなればなるほど、第２図に示すように
有効素子面積の割合が減してしまう。現在ｅ ４ｃｈ程
度がもっとも適当だといわれているが、それでも３２個
のＩＣが必要となる。Furthermore, for a display of approximately 1000 x 100 lines, approximately 64 ICs each having 32 channels of output transistors are required, making it necessary to mount a large number of ICs. Physically, the number of output transistors can be increased, but as the number of pins increases, the effective element area ratio decreases as shown in FIG. Currently, it is said that e4ch is the most suitable, but 32 ICs are still required.
発明が解決しようとする問題点
１０００Ｘ１０００本程度の大型フラットディスプレイ
を駆動するだめに、Ｅ５０ ＭＨｚ程度の転送速度およ
び１ｏｏｃｈ以上の出力トランジスタを有する駆動用Ｉ
Ｃが必要となる。そこで、転送速度の高速化および多ピ
ン化が課題となっている。Problems to be Solved by the Invention In order to drive a large flat display of about 1000 x 1000 lines, a driving I having a transfer rate of about E50 MHz and an output transistor of 1ooch or more is required.
C is required. Therefore, increasing the transfer speed and increasing the number of pins have become issues.
問題点を解決するだめの手段
フィルムキャリヤのインナーリードの両面に同じ機能を
有する半導体装置を実装し、しかも互いの電極位置が向
い合せた時に一致しないように配置する。Means for solving the problem Semiconductor devices having the same function are mounted on both sides of the inner lead of the film carrier, and the electrodes are arranged so that they do not coincide when facing each other.
作 用
フィルムキャリヤの両面に実装するために、実装面積を
増す事なく、データの転送速度および多ピン化を計る事
ができる。Since it is mounted on both sides of the working film carrier, it is possible to increase the data transfer speed and increase the number of pins without increasing the mounting area.
実施例 本発明の概略図を第１図に示す。Example A schematic diagram of the invention is shown in FIG.
フィルムキャリヤ１のインナーリード２の両面に第１の
半導体装置３と第２の半導体装置４が接続された構造に
なっている。The structure is such that a first semiconductor device 3 and a second semiconductor device 4 are connected to both sides of an inner lead 2 of a film carrier 1.
同図ａは、フィルムキャリヤ１のインナーリード２を示
しており、１本おきに第１および第２の半導体装置の出
力トランジスタに対応するようになっており、第１の半
導体装置３が奇数番号のラインの場合、第゛２の半導体
装置４は偶数番号のラインを駆動する事になる。Figure a shows the inner leads 2 of the film carrier 1, and every other lead corresponds to the output transistors of the first and second semiconductor devices, with the first semiconductor device 3 being an odd-numbered one. In the case of lines, the second semiconductor device 4 drives even-numbered lines.
同図すは、第１および第２の半導体装置３，４を示して
おり、互いの電極位置が一致しないようになっておυ、
かさね合せた時、チドリ状だなるようになっている。The figure shows first and second semiconductor devices 3 and 4, and their electrode positions do not match, υ and 4.
When stacked together, it looks like a plover.
同図Ｃ接続した時の構造を示す。半導体装置３゜４の電
極上には金属突起Ｓが形成されており、この金属突起６
を介してインナーリード２と接合されている。The figure shows the structure when C is connected. A metal protrusion S is formed on the electrode of the semiconductor device 3.4, and this metal protrusion 6
It is connected to the inner lead 2 via.
次に具体例について説明する。Next, a specific example will be explained.
フィルムキャリヤ１は１２５μｍ厚のポリイミド上に３
６μｍ 厚の銅箔のパターンが形成されており、表面は
錫メッキされている。インナーリード２は、第１の半導
体装置３の電極群を第２の半導体装置４の電極群に相対
する位置に形成されている。The film carrier 1 is 3 on a 125 μm thick polyimide.
A 6 μm thick copper foil pattern is formed, and the surface is tin-plated. The inner lead 2 is formed at a position where the electrode group of the first semiconductor device 3 faces the electrode group of the second semiconductor device 4.
第１および第２の半導体装置３，４は、シフトレジスタ
、ランチそして出力トランジスタの機能を有しており、
大きさは、第１の半導体装置３の方を大きくしてあり、
電極群は、互いにかさなり合わないようにチドリ状に形
成した。Ａｌ電極の上にＴｉ とＰｄのバリアメタルを
介してメッキ法によりＡｕ突起電極５を形成した。デー
タの転送速度は、１０ＭＨｚ 、出力トランジスタは６
４ｃｈを有している。The first and second semiconductor devices 3 and 4 have the functions of a shift register, a launch, and an output transistor,
The first semiconductor device 3 is larger in size,
The electrode group was formed in a staggered shape so as not to overlap each other. An Au protruding electrode 5 was formed on the Al electrode by a plating method via a barrier metal of Ti and Pd. Data transfer speed is 10MHz, output transistor is 6
It has 4ch.
フィルムキャリヤ１との接続は、大きさの小さい第２の
半導体装置４を先に行ない、Ａｕの突起電極と錫メッキ
のリード間にＡｕＳｎの合金を形成し接続しそののち、
フィルムキャリヤ１を反転し、第１の半導体装置３を接
続した。つまり、データの転送速度２０ＭＨｚ 、出力
トランジスタは１２ｓｃｈを有する事になる。The connection to the film carrier 1 is made by first connecting the second semiconductor device 4, which is smaller in size, by forming an AuSn alloy between the Au protruding electrode and the tin-plated lead, and then connecting.
The film carrier 1 was inverted and the first semiconductor device 3 was connected. In other words, the data transfer rate is 20 MHz and the output transistor has 12 sch.
このようにして作成した半導体装置を用いてデー）側電
極１０２４本、スキャン側電極７６８本を有するＥＬデ
ィスプレイを駆動電圧１００Ｖで駆動した。ＥＬディス
プレイは、データ側、スキャン側ともて電極は、上下お
よび左右に一本おきにより分けており、データ側は６１
２本が上下に、スキャン側は３８４本が左右にふり分け
て形成されている。つまり、実際には、データの転送速
度４０ＭＨｚで駆動でき、半導体装置の数もデータ側で
８ヶ、スキャン側で６ケで駆動できた。Using the semiconductor device thus produced, an EL display having 1024 data side electrodes and 768 scan side electrodes was driven at a driving voltage of 100V. In the EL display, the data side, scan side, and front electrodes are separated by every other electrode on the top and bottom and left and right, and the data side has 61 electrodes.
There are 2 wires on the top and bottom, and 384 wires on the scan side, distributed left and right. That is, in reality, it was possible to drive at a data transfer rate of 40 MHz, and the number of semiconductor devices was eight on the data side and six on the scan side.
実施例では、フィルムキャリヤのリードに錫メツキされ
たものを用いたが、これに限定されるものではなく、金
メッキでも良い０また、突起電極の材質も金に限定され
るものではなく、鉛−錫の合金でも良くその形成方法も
メッキ法に限定されず蒸着法でも良い。つまり、フィル
ムキャリヤと突起電極とは、Ａｕ−３ｎやＡ ｕ −Ａ
ｕの接合により行なわれる。In the example, the leads of the film carrier were plated with tin, but the material is not limited to this and may be plated with gold.Also, the material of the protruding electrodes is not limited to gold, but may be lead-plated or lead-plated. It may be an alloy of tin, and its formation method is not limited to the plating method, but may also be a vapor deposition method. In other words, the film carrier and the protruding electrodes are Au-3n, Au-A
This is done by joining u.
また、実施例ではＥＬディスプレイを用いたが、液晶デ
ィスプレイやプラズマディスプレイにも応用できる。Further, although an EL display is used in the embodiment, it can also be applied to a liquid crystal display or a plasma display.
発明の効果
−つのフィルムキャリヤの両面に同じ機能を有する駆動
用ＩＣを実装する事だより、同じ実装面積で２倍の出力
トランジスタを有する事ができ、さらにデータの転送速
度も２倍にできるため大型で電極数の多いフラットディ
スプレイにも対応する事ができる。Effects of the invention - By mounting drive ICs with the same function on both sides of a single film carrier, it is possible to have twice as many output transistors in the same mounting area, and also double the data transfer speed. It can also be used for large flat displays with a large number of electrodes.
第１図ａおよびｂは本発明の一実施例における半導体装
置の要部を示す平面図、第１図Ｃは同断面図、第２図は
端子数の増加に伴なう有効素子面積の割合の減少を示す
平面図である。
１・・・・・・フィルムキャリヤ、２・・・・・・イン
ナーリード、３・・・・・・第１の半導体装置、４・・
・・・・第２の半導体装置、６・・・・・・突起電極。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名／−
−−フィルム午イリャ
（６ン
（Ｃジ
第２図1A and 1B are plan views showing essential parts of a semiconductor device according to an embodiment of the present invention, FIG. 1C is a sectional view of the same, and FIG. 2 is a ratio of effective element area as the number of terminals increases. FIG. DESCRIPTION OF SYMBOLS 1... Film carrier, 2... Inner lead, 3... First semiconductor device, 4...
. . . second semiconductor device, 6 . . . protruding electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person/-
--Film No. 6 (Cji 2nd figure)
Claims (3)
を有し、入力信号用電極群と出力信号用電極群が周縁に
形成された第１の半導体装置と、前記第１の半導体装置
と同一機能を有し、入力信号用電極群と出力信号用電極
群とが前記第１の半導体装置の電極群とは異なる位置に
形成された第２の半導体装置と、インナリードが前記第
１および第２の半導体装置の入力信号用電極群と出力信
号用電極群と相対する位置まで延在されているフィルム
キャリヤからなり、前記フィルムキャリヤの前記第１の
半導体装置の電極群と相対するインナーリードと前記第
１の半導体装置の電極群とが接続され、前記フィルムキ
ャリヤの前記第２の半導体装置の電極群と相対するイン
ナーリードと、前記第２の半導体装置の電極群とが、前
記第１の半導体装置が接続された反対面で接続されてい
る事を特徴とする半導体装置。(1) A first semiconductor device that has a shift register, a latch, and an output transistor, and has an input signal electrode group and an output signal electrode group formed on its periphery, and has the same function as the first semiconductor device. , a second semiconductor device in which an input signal electrode group and an output signal electrode group are formed at different positions from the electrode groups of the first semiconductor device; and an inner lead is formed in the first and second semiconductor devices. a film carrier extending to a position facing the input signal electrode group and the output signal electrode group, and an inner lead of the film carrier facing the electrode group of the first semiconductor device; The first semiconductor device is connected to an inner lead of the film carrier facing the electrode group of the second semiconductor device, and the electrode group of the second semiconductor device is connected to the first semiconductor device. A semiconductor device characterized in that the semiconductor device is connected on opposite sides.
起が形成された事を特徴とする特許請求の範囲第１項記
載の半導体装置。(2) The semiconductor device according to claim 1, wherein metal protrusions are formed on the electrode groups of the first and second semiconductor devices.
徴とする特許請求の範囲第２項記載の半導体装置。(3) The semiconductor device according to claim 2, wherein the metal protrusion is made of gold and a tin-lead alloy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23734686A JPS6392034A (en) | 1986-10-06 | 1986-10-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23734686A JPS6392034A (en) | 1986-10-06 | 1986-10-06 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6392034A true JPS6392034A (en) | 1988-04-22 |
Family
ID=17014026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23734686A Pending JPS6392034A (en) | 1986-10-06 | 1986-10-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6392034A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6664618B2 (en) | 2001-05-16 | 2003-12-16 | Oki Electric Industry Co., Ltd. | Tape carrier package having stacked semiconductor elements, and short and long leads |
| JP2009064854A (en) * | 2007-09-05 | 2009-03-26 | Nec Electronics Corp | Lead frame, semiconductor device, and manufacturing method of semiconductor device |
-
1986
- 1986-10-06 JP JP23734686A patent/JPS6392034A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6664618B2 (en) | 2001-05-16 | 2003-12-16 | Oki Electric Industry Co., Ltd. | Tape carrier package having stacked semiconductor elements, and short and long leads |
| JP2009064854A (en) * | 2007-09-05 | 2009-03-26 | Nec Electronics Corp | Lead frame, semiconductor device, and manufacturing method of semiconductor device |
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