JPS6391785A - Parallel processing type data collation processor - Google Patents

Abstract

PURPOSE:To easily discriminate a processor in which an error is generated, by switching a processing to a serial processing which indicates the collation of the same data for all of the processors of same types, and performing the checking of the coincidence of operations among the processors of the same types. CONSTITUTION:When a signal CHG goes to a logic 1, a data distribution control part 12 checks control signal lines 1a-1f between the processor, and reads out a collation data in a memory 13 to a register 15, and distributes it to all of the first processors with the same timing through a common bus 200, and the serial processing is started. Collating operation timing coincidence check signals 2a-2d from the first processors, and the collating operation timing coincidence check signals 3a and 3b from second processors, are checked for their coincidence at comparators C3 and C4, respectively, and when discrepancy is detected, an error detection signal e1 goes to the logic 1 by gates G3, and G4. In this way, it is possible to easily discriminate the processor in which the abnormality of an operation is generated, from the output of an operation timing holding register 16.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel processing type data collation processing device that collates one piece of search data and a large amount of file data at high speed.

[Conventional technology]

Data matching is a process of matching search data and file data using a certain algorithm in order to extract data that matches or is similar to search data from a large amount of file data.

For example, in the case of fingerprint matching, the search fingerprint data collected from the crime scene and the file fingerprint data of multiple people who have been stamped and registered in advance are compared using their respective feature points as keys, and the number of matching points is set in advance. Restore the holder of the file fingerprint data that exceeds the threshold.

In order to speed up such data matching, a method has been adopted in which multiple types of processors based on matching algorithms are connected to perform parallel processing. In this method, each processor performs one piece of data verification, and the verification time also differs depending on the content of the verification data. Therefore, one method for supplying a large amount of file data to each processor is to check all the data sent from the outside and the operating status of the processor at that time, and then decide based on a certain priority among idle processors. There is a method of sending the information to the processor and instructing it to check.

[Problem that the invention seeks to solve]

In such a conventional verification data distribution method.

Although the matching results will be stored in the final processor after being processed by several processors.

When an error is detected in the data related to verification in the final processor, it is generally difficult to point out the processor that caused the error, and a large amount of time is spent searching for the cause. These drawbacks tend to become more pronounced as the degree of parallelism of the processor increases.

Furthermore, in such a parallel processing system, even if the same data is collated again, there is no guarantee that the flow of data will be exactly the same due to various factors.

Furthermore, there is a problem in that extracting and comparing pairs of search data and file data in which data errors have been detected from a large amount of data increases the burden on the software.

The present invention aims to solve the above-mentioned problems of the conventional devices and to provide a data collation processing device that can easily identify a processor that is the source of an error among a plurality of processors.

[Failure to solve the problem]

In the parallel processing type data collation processing device of the present invention, a plurality of processors having the same function are connected in cascade.

Means for specifying a method of distributing verification data to each processor in a data verification processing device that performs parallel processing in which each processor performs data verification.

and an identification information comparing means that compares the identification information in the verification data with preset identification information and generates a matching signal.

When serial processing is specified as the verification data distribution method, when the identification information matching signal is generated, the system waits for all processors to complete their operations at that point, and then supplies matched verification data to all processors with the same function at the same timing. a means for monitoring the matching check signal of matching operation timing selected in advance and transmitted from all processors; and a means for holding the matching check signal of matching timing of the matching operation when a mismatch signal is generated by the monitoring means. means.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram showing a parallel processing type data collation processing device according to an embodiment of the present invention, and FIG. FIG. In FIG. 1, four first matching processors 20 to 2 having the same configuration serve as parallel matching processors.
37! Second collation processor 30 with the same configuration in the two γ-domains
．． 31 are connected via common buses 200 and 300.

10 is a control signal 101 from the outside via a common bus 100.
11 is a verification data serial processing detecting section. The data distribution unit 10 also has a function of reading the final verification results stored in the second verification processors 30 and 31 via the common bus 400 and transmitting them to the outside via the common path 100.

First, a method for parallel processing of data collation of N pieces of file data for one piece of search data will be briefly explained.

In FIG. 1, search data sent via an external common bus 100 under the control of an external control signal 101 is stored in a verification data storage section 13 in a verification data distribution section 10. Next, the data distribution control unit 12 sends the first all-matching processors 20 to 23 and the second all-matching processor 30.31.
Commonly sends search data to. Next, external common bus 1
After the file data sent out one by one via 00 is stored in the collation data storage unit 13, the busy state of the first collation processors 20 to 23 is checked, and one idle first collation processor is stored. 1 Sends one file data to the selected processor and instructs it to be verified.

In the following, the file data that is sent one by one is selected and collated by the first processor. When all the first processors are in the ping state, it is natural to wait until an idle processor occurs.

A data transfer request from the first matching processor to the second matching processor then causes a similarly idle second matching processor to
A matching processor is selected, and data is transferred to the selected processor via the common bus 300 to instruct matching. That is,
The verification instruction to the first verification processor via the common bus 200 and the verification instruction from the first verification processor to the second verification processor via the common bus 300 are processed in parallel. When the collation process of N file data is completed in each processor, the collation results in the second processor are sequentially read out via the common bus 400 and sent to the outside via the common path 100. The above is the data matching sequence in normal parallel processing.

Next, referring to FIG. 2, 12 is a data distribution control section;
This is the part that controls the generation of various control signals and the distribution of data. Register S1 is a register that stores the identification number of search data set in advance before the start of matching, and register F1
is a register that stores a preset identification number of file data, and register S2 is a register that stores an identification number of file data that has been set in advance.
Register F2, which is a register for storing a different number, transfers file data to the memory 13 via the common bus 100 at the time of verification.
This is a register that stores the identification number at the same time as the storage. Comparator C1 compares the contents of registers S1 and 82, and when they match, signal 111 goes to logic "1"; comparator C2 compares the contents of registers F1 and F2, and when they match, signal 112 goes to logic In other words, if a preset combination of search data and file data appears at the start of matching, the output of KE (-)Gl becomes logic "1".

The signal DM is a signal that specifies the collation processing method for the processor, and when the logic is "0", it instructs the above-mentioned parallel processing method, and when the logic is "1", it instructs the serial processing method.What is serial processing in the present invention? , one file data is first commonly distributed to all the first matching processors for matching at the same timing, and then the data in the first matching processor is transferred to the second matching processors at the same timing. It means to execute the same verification, and it means to proceed with the process while waiting for the next file data verification until all processors finish verification at the same time.

Therefore, when the signal CHG becomes logic "1", the data allocation j control unit 12 connects the control signal lines la to If with the processor.
(a collection of pinot signals and request signals), and controls the verification data storage address control unit 14 to check the verification data in the memory 13.

It is read out to the register 15 and distributed to all the first processors 20 to 23 at the same timing via the common path 200. When serial processing starts, signal line 11
5 becomes logic °l''.

2a, 2b, 2c, and 2d are first processors 20 to 23;
This is the verification operation timing match check signal from 3.
a and 3b are verification operation timing coincidence check signals from the second processor 30 and 31, and the comparators C3 and 3b respectively
A match check is performed in C4, and if a match is detected, the signal lines 113 and 114 become logic "1", and gate G3
．． G4 causes the error detection signal e1 to become logic "1". In other words, if all the processors successfully collate the same collation data at the same timing, the error detection signal e1 becomes logic ``'0''.
It should be. The nostar 16 for holding the operation timing mismatch signal is a register that stores and holds the operation timing match check signal from each processor when the error detection signal is at logic "1".

Therefore, the output 1 of this operation timing holding register 16
16, it becomes possible to easily determine which processor is malfunctioning. The identification number of the verification data is shown in FIG. 3 as an example.

An example of the verification operation itself will be described using the numbers assigned to each verification data. BSYi (i = 0 to 3) is a control line that indicates whether the first processor is in the busy state or idle state, and BSYJ (j = 4, 5) is a control line that indicates whether the second processor is in the pinot state or idle state. The control line shown, RQU
i (t~0~3) is the common bus 2o.

RQLi (i = Q~3) is the request control line for data transfer from the first processor to the second processor + RQP3 (j ” O) 1)
is a request control line that instructs data transfer to the second processor. Block 12a is a first processor distribution determining unit that determines the first processor when collating data in the memory 13 is distributed to the first processor, and block 12b is when distributing data from the first processor to the second processor. The first . This is a second norocessor determining unit.

When the signal CHG is at logic "0", if verification data exists in the verification data storage section 13, the signal RQ becomes logic "1". At this time, the BSYi signal from the processor of cylinder 1 is checked, the first processor whose BSYi signal is logic "On" (idle state) and whose number is smaller is selected, and the RQUi signal corresponding to the corresponding processor is set to logic "1". data transfer.

On the other hand, when the signal CHG is at logic "1" and verification data exists in the memory 13, the BSY from each first processor
The i signal and the BSYj signal from each second processor are checked, and when all processors are in an idle state, an RQ is sent to instruct the data transfer to the first processor.
All Ui signals are set to logic "1". The above is the first
This is the operation of the data distribution system of the processor distribution determining unit 12a.

Next, the first. The operation of the data distribution system of the second f-row sensor determining section 12b will be explained. When the signal CHG is logic “0”, the first
When a data transfer request from one processor to a second processor is requested by the RQL i signal.

Check the BSYj signal from the second processor.

If there is an idle second processor, the RQLi signal is logic ``1'' and the first processor with the lower number is selected, and the ACKi signal reports acceptance of the request, and the BSYj signal is the logic ``10'' and the lower number is selected. Select a second processor and set the corresponding RQPj signal to logic
Set it to '1' to instruct data transfer.

When the signal CHG is logic "1", the #RQLi signals all become logic "1" at the same time, so the ACKi signal and P
, QPj signals are all simultaneously set to logic ``1#'' to indicate data transfer from the first processor to the second processor.

〔Effect of the invention〕

As explained above, (1) the present invention has the following advantages: (1) In collating a large amount of data in normal parallel processing, a pair of preset search data and file data is detected at the time when the pair is actually to be collated, and at that point the same type of data is detected. By switching to serial processing that instructs all of the processors to match the same data, and checking the consistency of the operations between the same processors, it is possible to easily and without compromising performance from among multiple processors. This has the effect of being able to identify the processor where the error occurred.

Conversely, if an error is detected by a processor with parallel processing, and no action matching error occurs as a result of processing the illuminant data according to the present invention, the processor will be able to process the data regardless of whether it is performing the same processing. Since errors are commonly occurring, it also has the effect of being able to be determined to be a logic bug rather than a processor-specific failure.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an embodiment of the parallel processing type data collation processing device of the present invention, FIG. FIG. 3 is a diagram for explaining collation data, and FIG. 4 is a block diagram showing the functions of the data distribution control section of FIG. 2. Explanation of symbols = 10 is a verification data distribution unit, 11 is a serial processing detection unit, 12 is a data distribution control unit, 13 is a verification data storage unit, 14 is a verification data storage address control unit, 15 is a verification data transfer renostar, 16 is a verification data transfer renostar Zosta for holding operation timing mismatch signal. Otsu 20 to 23 are first matching processors, 30431 is a second matching processor, Sl, S2. Fl. F2 is 2L"'+Russo star, C1 to C4 are comparators, Gl to G4 are logic keys "-), 10.0°200
．． 300. '400 is a common data bus line. 101, la to if are control signal lines, 2a to 2d; 3a and 3b represent operation timing coincidence signal lines, respectively. Figure 2 //)/

Claims (1)

[Claims] 1. In a parallel processing type data collation processing device in which a plurality of processors having the same function are connected in cascade and each processor collates data, there is a means for specifying the distribution method of collation data to each processor, and a means for specifying the distribution method of collation data to each processor, an identification information comparing means that compares the identification information with preset identification information and generates a matching signal; Means for supplying matched verification data to all processors having the same function at the same timing after waiting for the end of the operation to instruct verification, and checking for matching of verification operation timings and monitoring signals selected and sent from all processors in advance and means for holding the matching operation timing coincidence check signal when the monitoring means detects the matching signal.