JPS6390895A - Multilayer interconnection board unit - Google Patents
Multilayer interconnection board unitInfo
- Publication number
- JPS6390895A JPS6390895A JP23619986A JP23619986A JPS6390895A JP S6390895 A JPS6390895 A JP S6390895A JP 23619986 A JP23619986 A JP 23619986A JP 23619986 A JP23619986 A JP 23619986A JP S6390895 A JPS6390895 A JP S6390895A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- layer
- insulating layer
- interlayer insulating
- conductor portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 50
- 239000010410 layer Substances 0.000 claims description 49
- 239000011229 interlayer Substances 0.000 claims description 15
- 239000012790 adhesive layer Substances 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 description 8
- 239000010408 film Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000006260 foam Substances 0.000 description 1
- 150000002343 gold Chemical class 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電子写真プリンタに用いられる発光ダイオー
ド（以下ＬＥＤと略称する）ヘッドなどを形成するのに
好適な多層配Ｉ２基板体に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer I2 substrate suitable for forming a light emitting diode (hereinafter abbreviated as LED) head used in an electrophotographic printer.
前述したＬＥＤヘッドは、−１２に、基板体に１、 Ｅ
Ｄアレイを搭載して形成されるが、安価に製）告でき
しかも放熱性も良好な基板体として第２図に示すものが
近年開発されている。The above-mentioned LED head has -12, 1 and E on the substrate body.
In recent years, a substrate body shown in FIG. 2 has been developed which is formed by mounting a D array, can be manufactured at low cost, and has good heat dissipation properties.
第２図において、アルミニウム桔板１上にはアルマイト
層２が形成されており、このアルマイト層２上には、ス
パッタリングまたは蒸着等の薄膜技術によりアルミニウ
ムを成膜し、この成膜されたアルミニウムの薄膜をフォ
トプロヒスにより所定のパターンに形成してなる導ｔ４
）Ｎ ３がＦＡ層されている。また、この導体層３上
には、絶縁層４および金めつき層５が選択的に積層され
ており、このうち絶縁層４と間隔を隔てた中央部の金め
つき層５上にはＧａＡＳＰ等の多数の１． Ｆ Ｄアレ
イ６がダイボンディングまたは導電慴接着剤により載置
固定されている。さらに、前記絶縁層４には、ポリイミ
ド等の感光性または非感光性樹脂をスクリーン印刷また
はスピナ等により形成してなる層間絶縁層７が積層され
ており、この層間絶縁層７上には、層間絶縁層７により
１）０記尋体層３との間を絶縁された他の導体層８が前
記導体層３と同様の工程により積層されている。この導
体層８は、その一部が前記絶縁層４と接合されており、
また、前記ＬＥＤアレイ６にス・ｊ向する部位の導体層
８」二にはソイＡｌボンディング用のパッドおよび外部
取出し端子となる他の金めっきｖ４９が積層され、この
金めつき層９と前記ＬＥＤアレイ６との間には多数のワ
イヤ１０が架設されている。なお、外部に露出している
導体層８および層間絶縁層７の外側（，１保護層１１に
より被覆されている。In FIG. 2, an alumite layer 2 is formed on an aluminum plate 1, and an aluminum film is formed on this alumite layer 2 by a thin film technique such as sputtering or vapor deposition. A conductor t4 formed by forming a thin film into a predetermined pattern using photoprohythm.
)N3 is FA layered. Furthermore, an insulating layer 4 and a gold-plated layer 5 are selectively laminated on the conductor layer 3, and GaASP is formed on the gold-plated layer 5 in the center spaced apart from the insulating layer 4. Many 1. The FD array 6 is mounted and fixed by die bonding or conductive adhesive. Furthermore, an interlayer insulating layer 7 formed of photosensitive or non-photosensitive resin such as polyimide by screen printing or a spinner is laminated on the insulating layer 4. Another conductor layer 8 insulated from the 1) zero-cross conductor layer 3 by the insulating layer 7 is laminated by the same process as the conductor layer 3. A part of this conductor layer 8 is joined to the insulating layer 4,
Further, another gold plating V49 is laminated on the conductor layer 8''2 of the portion facing the LED array 6 in the direction S and J, and this gold plating layer 9 and the above-mentioned A large number of wires 10 are installed between the LED array 6 and the LED array 6. Note that the outside of the conductor layer 8 and the interlayer insulating layer 7 exposed to the outside are covered with a protective layer 11.
前記導体層８は、具体的には、第３図に丞すように、第
１導体部８ Ａ ａ３よび第２導体部８Ｂにより構成さ
れて４３す、このうち第１導体部８Δは、前記層間絶縁
層７より薄厚とされ１）を記絶縁層４上に直接積層され
、第２導体部８Ｂは、これらの第１２＃体部８Ａおよび
層間絶縁層７を被覆するように積層されている。Specifically, the conductor layer 8 is composed of a first conductor part 8Aa3 and a second conductor part 8B, as shown in FIG. The second conductor portion 8B is thinner than the interlayer insulating layer 7 and is laminated directly on the insulating layer 4 mentioned above. .
しかしながら、前述した導体層８は、第１導体部８Ａが
層間絶縁層７より薄厚であるため、第２導体部８Ｂの積
Ｖ峙に第１導体部８Ａ上の第２導体部８Ｂの上部に四部
１２が形成され、このため第３図にＯ印で示した四部１
２の周縁の第２導体部８Ｂのエツジ部１３において第２
導体部８Ｂが切断されるおそれがある。However, in the conductor layer 8 described above, since the first conductor part 8A is thinner than the interlayer insulating layer 7, the upper part of the second conductor part 8B on the first conductor part 8A is A quadrilateral 12 is formed, so that the quadrilateral 1 marked O in FIG.
At the edge portion 13 of the second conductor portion 8B on the periphery of the second
There is a risk that the conductor portion 8B may be cut.
本発明は、このように点に鑑み、第２導体部に切断のお
それがなく、信頼性の高い多層配線基板体を提供するこ
とを目的とする。In view of the above points, it is an object of the present invention to provide a highly reliable multilayer wiring board body in which there is no fear of cutting the second conductor portion.
前述した問題点を解決するため、本発明は、絶縁層上に
層間絶縁層およびこの層間絶縁層より薄厚の第１導体部
を選択的に積層し、これらの居間絶ｎ層および第１導体
部上に第２導体部を積層してなる多層配線基板体におい
て、前記第１導体部および第２導体部間に接着層を介装
し、第１３ｉＪ体部および接着層の合計厚みを層間絶縁
層の厚みに雪しくしたことを特徴としている。In order to solve the above-mentioned problems, the present invention selectively laminates an interlayer insulating layer and a first conductor portion thinner than this interlayer insulating layer on an insulating layer, In a multilayer wiring board body formed by laminating a second conductor portion thereon, an adhesive layer is interposed between the first conductor portion and the second conductor portion, and the total thickness of the 13iJ body portion and the adhesive layer is equal to the interlayer insulating layer. It is characterized by its thickness, which resembles snow.
本発明によれば、第２導体部を完全に平面状にの積層で
きるので、第２導体部に凹部の生じるおそれがなく、第
２導体部の切断を未然に防止することができる。According to the present invention, since the second conductor part can be stacked completely in a plane, there is no fear that a recess will be formed in the second conductor part, and it is possible to prevent the second conductor part from being cut.
〔実施例） 以下、本発明を図面に示す実施例により説明する。〔Example) The present invention will be explained below with reference to embodiments shown in the drawings.
第１図は本発明に係る多層配線基板体の要部を示すもの
であり、絶縁層４上には層間絶縁層７および導体層８の
第１導体部８△が選択的に積層されている。このうち第
１導体部８△は、スパッタリングまたは蒸着等のλ９膜
技術によりアルミニウムを成膜し、フォ１−プ［１セス
により所定のパターンに形成したものであり、第１導体
部８Δの厚みは層間絶縁層７の厚みより肋くされている
。この第１導体部８Ａ十には、銅からなる接着層１４が
カッパライジング法により積層されており、第１導体部
８Ａおよび接着層１４の合計厚み番、王前記層間絶縁層
７の厚みと等しくされている。FIG. 1 shows the main parts of a multilayer wiring board body according to the present invention, in which an interlayer insulating layer 7 and a first conductor portion 8Δ of a conductor layer 8 are selectively laminated on an insulating layer 4. . Among these, the first conductor part 8Δ is formed by forming a film of aluminum using a λ9 film technique such as sputtering or vapor deposition, and is formed into a predetermined pattern by forming a film using a foam [1 process], and the thickness of the first conductor part 8Δ is thicker than the thickness of the interlayer insulating layer 7. An adhesive layer 14 made of copper is laminated on the first conductor part 8A by a copperizing method, and the total thickness of the first conductor part 8A and the adhesive layer 14 is equal to the thickness of the interlayer insulating layer 7. has been done.
前記カッパライジング法は、アルミニウム（１’）に塩
化銅（Ｃｕ２ＣｆＪ２）を塗イ１し、約４００〜４５０
℃の温度に加熱すると金属銅（Ｃｕ）が析出し、その一
部がアルミニウムに拡散して、アルミニウムと銅の均一
な金属間化合物を形成する方法であり、その反応式は上
記の通りである。In the copperizing method, aluminum (1') is coated with copper chloride (Cu2CfJ2), and the
It is a method in which metallic copper (Cu) precipitates when heated to a temperature of ℃, and a part of it diffuses into aluminum to form a uniform intermetallic compound of aluminum and copper, and the reaction formula is as above. .
加熱
２１→３ＣＵ２Ｃρ２→
６Ｃｕ＋２△、ｌｌＣ！Ｊ３
このようなカッパライジング法により第１導（本部８Ａ
上に積層された接着Ｆｉ １４の１−面と絶縁層４の上
面とは同一平面とされており、これらの絶縁層４および
接着層１４上には第２力体部８Ｂが第１導体部８Ａと同
様の工程により積層されている。Heating 21→3CU2Cρ2→6Cu+2△,llC! J3 The first conductor (Headquarters 8A
The first surface of the adhesive Fi 14 laminated thereon and the upper surface of the insulating layer 4 are on the same plane, and the second force body part 8B is placed on the first conductor part on the insulating layer 4 and the adhesive layer 14. It is laminated by the same process as 8A.
前）ホした構成によれば、導体層８の第２導体部８Ｂが
完全な平面状態で積層されるので、この第２導体部８Ｂ
に第３図のような凹部１２が形成されることがなく、し
たがって導体層８の第２導体部８Ｂが切断されるおそれ
がない。このｖＬ宋、信頼性が増して歩留りが向上し、
安価に製造することができる。According to the configuration described above, the second conductor portion 8B of the conductor layer 8 is laminated in a completely flat state, so that the second conductor portion 8B
A recess 12 as shown in FIG. 3 is not formed in this case, and therefore there is no possibility that the second conductor portion 8B of the conductor layer 8 will be cut. This vL Song has increased reliability and improved yield,
It can be manufactured at low cost.
なお、本発明は、前述した実施例に限定されるものでは
なく、種々の変更が可能である。Note that the present invention is not limited to the embodiments described above, and various modifications are possible.
以上説明したように本発明によれば、第２導体部の切断
のおそれがなく、信頼性を向上することができるという
優れた効果を秦することができる。As explained above, according to the present invention, there is no fear of cutting the second conductor portion, and the excellent effect of improving reliability can be achieved.
第１図は本発明に係る多層配線基板体の実施例を示す要
部の縦断面図、第２図は既開発の１． Ｅ ｒ）ヘッド
の縦断面図、第３図は第２図の要部の拡大図である。
１・・・アルミニウム基板、２・・・アルマイト層、３
・・・導体層、４・・・絶縁層、５・・・金めつき層、
６・・・Ｌ Ｅ Ｄアレイ、７・・・層間絶縁層、８・
・・導体層、８Δ・・・第１導体部、８Ｂ・・・第２ク
グ体部、９・・・金めつき層、１０・・・ワイヤ、１１
・・・保護層、１２・・・凹部、１３・・・エツジ部、
１４・・・接着層。FIG. 1 is a longitudinal cross-sectional view of the main part showing an embodiment of the multilayer wiring board body according to the present invention, and FIG. Er) Longitudinal sectional view of the head, FIG. 3 is an enlarged view of the main part of FIG. 2. 1... Aluminum substrate, 2... Alumite layer, 3
...conductor layer, 4...insulating layer, 5...gold plating layer,
6... LED array, 7... Interlayer insulating layer, 8.
...Conductor layer, 8Δ...First conductor part, 8B...Second pole body part, 9...Gold plating layer, 10...Wire, 11
...protective layer, 12...recessed part, 13...edge part,
14...adhesive layer.
Claims (1)
薄厚の第１導体部を選択的に積層し、これらの層間絶縁
層および第１導体部上に第２導体部を積層してなる多層
配線基板体において、前記第１導体部および第２導体部
間に接着層を介装し、第１導体部および接着層の合計厚
みを層間絶縁層の厚みに等しくしたことを特徴とする多
層配線基板体。 ２） 前記両導体部はアルミニウムからなり、前記接着
層は銅からなることを特徴とする特許請求の範囲第１項
記載の多層配線基板体。[Claims] 1) An interlayer insulating layer and a first conductor portion thinner than the interlayer insulating layer are selectively laminated on the insulating layer, and a second conductor portion is formed on the interlayer insulating layer and the first conductor portion. In the multilayer wiring board body formed by laminating the above, an adhesive layer is interposed between the first conductor part and the second conductor part, and the total thickness of the first conductor part and the adhesive layer is made equal to the thickness of the interlayer insulating layer. A multilayer wiring board body characterized by. 2) The multilayer wiring board body according to claim 1, wherein both the conductor portions are made of aluminum, and the adhesive layer is made of copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23619986A JPS6390895A (en) | 1986-10-06 | 1986-10-06 | Multilayer interconnection board unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23619986A JPS6390895A (en) | 1986-10-06 | 1986-10-06 | Multilayer interconnection board unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6390895A true JPS6390895A (en) | 1988-04-21 |
Family
ID=16997247
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23619986A Pending JPS6390895A (en) | 1986-10-06 | 1986-10-06 | Multilayer interconnection board unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6390895A (en) |
-
1986
- 1986-10-06 JP JP23619986A patent/JPS6390895A/en active Pending
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