JPS6390893A - Method of forming multilayer interconnection - Google Patents

Method of forming multilayer interconnection

Info

Publication number
JPS6390893A
JPS6390893A JP23575686A JP23575686A JPS6390893A JP S6390893 A JPS6390893 A JP S6390893A JP 23575686 A JP23575686 A JP 23575686A JP 23575686 A JP23575686 A JP 23575686A JP S6390893 A JPS6390893 A JP S6390893A
Authority
JP
Japan
Prior art keywords
polyimide resin
substrate
layer
coating
intermediate insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23575686A
Other languages
Japanese (ja)
Inventor
健一 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP23575686A priority Critical patent/JPS6390893A/en
Publication of JPS6390893A publication Critical patent/JPS6390893A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路等に用いられる多層配線構造の形
成方法に係り、特に多層配線層間の中間絶縁に用いるポ
リイミド層の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a multilayer wiring structure used in a hybrid integrated circuit or the like, and particularly to a method for forming a polyimide layer used for intermediate insulation between multilayer wiring layers.

〔従来の技術〕[Conventional technology]

混成集積回路等に用いられる多層配線構造においては各
配線層間の中間絶縁層として有機物膜、特にポリイミド
樹脂がしばしば用いられる。これは酸化シリコン膜、窒
化シリコン膜の如き無機物膜が、通常CVD法、スパッ
タリング法等真空装置内で形成する必要があるため設備
が大規模化するのに比べ、ポリイミド樹脂膜はそのよう
な設備を必要とせず、比較的簡易な方法で形成できる利
点があることによる。
In multilayer wiring structures used in hybrid integrated circuits and the like, organic films, particularly polyimide resins, are often used as intermediate insulating layers between wiring layers. This is because inorganic films such as silicon oxide films and silicon nitride films usually need to be formed in vacuum equipment using CVD or sputtering methods, which requires large-scale equipment, whereas polyimide resin films require large-scale equipment. This is because it has the advantage that it can be formed by a relatively simple method without requiring.

ポリイミド樹脂から成る有機物膜を基板上の配線層と配
線層の間に介在する中間絶縁層として用いる場合、その
コーティング方法としてローラ・コーティング法、スピ
ン・コーティング法、スクリーン印刷法などがある。
When an organic film made of polyimide resin is used as an intermediate insulating layer interposed between wiring layers on a substrate, coating methods include roller coating, spin coating, and screen printing.

ローラ・コーティング法は第2図にその概略を示すよう
に、例えば3個のローラ24.25.26の組合せによ
り、ローラ24.25の間にためられたポリイミド樹脂
23を搬送路22ヒを搬送される少なくとも第1配線層
を設けた基板21上にローラ25.26により転写させ
るよう構成されている。
As schematically shown in FIG. 2, the roller coating method uses a combination of, for example, three rollers 24, 25, and 26 to transport the polyimide resin 23 accumulated between the rollers 24, 25 through the transport path 22. The image forming apparatus is configured to be transferred by rollers 25 and 26 onto a substrate 21 provided with at least a first wiring layer.

スピン・コーティング法は少なくとも第一配線層を設け
た基板上にポリイミド樹脂を置き基板ごと回転させるこ
とにより該樹脂を均一に被覆する方法である。
The spin coating method is a method in which a polyimide resin is placed on a substrate provided with at least a first wiring layer, and the entire substrate is rotated to uniformly coat the resin.

スクリーン印刷法はスクリーンメツシュを通して少なく
とも第一配線層を設けた基板上に溶剤に熔かした樹脂を
被覆するものである。
In the screen printing method, a resin dissolved in a solvent is coated on a substrate provided with at least a first wiring layer through a screen mesh.

第3図にこれらの方法で被覆した中間絶縁層を介在させ
た多層配線の一例を示す。まず絶縁基板1上に第1配線
層2 (例えばクロム)を被着し、バターニングした上
にポリイミド樹脂層3を被覆する(第3図(a))。次
にポリイミド樹脂層3の上にフォトレジスト4を被ri
、後所定のパターンをフォトマスクを用いて露光しく第
3図fbl)、所定のエツチング液でフォトレジスト4
とポリイミド(HjIhを同時にエツチングしスルーホ
ール5′を形成する(第3図(C))。フォトレジスト
4を除去後(第3図(d) )第2配線層5 (例えば
アルミニウム)を蒸着して多層配線を形成する(第3図
(e))。
FIG. 3 shows an example of multilayer wiring coated by these methods with an intermediate insulating layer interposed therebetween. First, a first wiring layer 2 (for example, chromium) is deposited on an insulating substrate 1, and then patterned and covered with a polyimide resin layer 3 (FIG. 3(a)). Next, a photoresist 4 is applied on top of the polyimide resin layer 3.
After that, a predetermined pattern is exposed using a photomask (FIG. 3 fbl), and the photoresist 4 is etched with a predetermined etching solution.
and polyimide (HjIh) to form a through hole 5' (FIG. 3(C)). After removing the photoresist 4 (FIG. 3(d)), a second wiring layer 5 (for example, aluminum) is deposited. Then, a multilayer wiring is formed (FIG. 3(e)).

〔発明が解決しようとする問題点〕 しかしこれら従来の中間絶縁層の被覆方法にはそれぞれ
次のような問題点がある。即ぢ、ローラ・コーティング
法によると、ポリイミド樹脂の粘度が高く、通常のレジ
ストコーティングローラではぬれ性が悪く被覆した基F
j、21にローラのすじがついてしまう。そのためロー
ラの形状の改良が試みられているが現状の技術ではその
ようなローラの作成は困難となっている。
[Problems to be Solved by the Invention] However, each of these conventional intermediate insulating layer coating methods has the following problems. According to the roller coating method, the viscosity of the polyimide resin is high, and it is difficult to wet the coated base F with a normal resist coating roller.
j, 21 has roller streaks. For this reason, attempts have been made to improve the shape of the roller, but it is difficult to create such a roller with current technology.

またスピン・コーティング法は均一に被覆出来る利点は
あるが回転台の上にコーティングすべき基板を置いてス
ピンさせる必要があり生産性が悪く、基板の大型化に対
応するには大規模な設備が必要となるという問題点があ
る。
In addition, spin coating has the advantage of being able to coat the substrate uniformly, but it requires placing the substrate to be coated on a rotating table and spinning it, resulting in poor productivity and the need for large-scale equipment to handle larger substrates. The problem is that it is necessary.

さらにスクリーン印刷法ではスクリーン印刷中にポリイ
ミド樹脂の溶剤が揮発してスクリーンメソシュの目づま
りを起こしてしまうことがある。
Furthermore, in the screen printing method, the solvent of the polyimide resin may evaporate during screen printing, causing clogging of the screen mesh.

また高密度化に伴い密なパターンの印刷には限界があり
、さらに被覆の表面にメソシュの形がついてしまい平坦
化されないという問題がある。
Furthermore, as the density increases, there is a limit to the printing of dense patterns, and there is also the problem that a mesoche shape forms on the surface of the coating, making it impossible to flatten it.

従って本発明の目的は有機物膜を中間絶縁層として被覆
する場合、大規模な設備を必要とせずに有機物膜を平坦
で均一な膜として被覆する方法を提供するものである。
Therefore, an object of the present invention is to provide a method for coating an organic material film as a flat and uniform film without requiring large-scale equipment when coating an organic material film as an intermediate insulating layer.

〔問題点を解決するための手段および作用〕本発明はロ
ーラ・コーティング等の通常の方法によってポリイミド
樹脂から成る有機物膜を形成した後紫外線をある一定時
間照射するものである。
[Means and operations for solving the problems] In the present invention, an organic film made of polyimide resin is formed by a conventional method such as roller coating, and then ultraviolet rays are irradiated for a certain period of time.

紫外線を照射することによって被覆されたポリイミド樹
脂層が平坦化され基板とのぬれ性がよくなり、ローラの
ずしもつがない中間絶縁層を形成することができる。
By irradiating the polyimide resin layer with ultraviolet rays, the coated polyimide resin layer is flattened and has good wettability with the substrate, making it possible to form an intermediate insulating layer with no roller gaps.

〔実施例〕〔Example〕

本発明の一実施例を第1図によって説明する。 An embodiment of the present invention will be described with reference to FIG.

例えば270mmX 60mmの大きさのガラス基板1
上に第1の絶縁層としてクロムII央2を蒸着によって
形成しフォトリソエツチングにより改定の形状にパター
ニングし、これに紫外線を3分間照射して基板表面をク
リーニングする。次に第2図に示すようなピッチ400
μm、深さ80μmの溝をもつローラを用いたローラ・
コーティング法によってポリイミド樹脂1! 3を約1
.5μmの厚さに塗布した(第1図(a))。
For example, a glass substrate 1 with a size of 270 mm x 60 mm
Chromium II layer 2 is formed as a first insulating layer thereon by vapor deposition, patterned into a revised shape by photolithography, and irradiated with ultraviolet rays for 3 minutes to clean the substrate surface. Next, the pitch 400 as shown in FIG.
A roller using a roller with grooves of μm and depth of 80 μm.
Polyimide resin 1 by coating method! 3 to about 1
.. It was applied to a thickness of 5 μm (FIG. 1(a)).

コーティング後直ちに25Wの低圧水銀ランプを6本使
用して紫外線を3分間照射した(第1図(b))。
Immediately after coating, ultraviolet rays were irradiated for 3 minutes using six 25W low-pressure mercury lamps (FIG. 1(b)).

その後135℃で30分間加熱した後フォトレジスト4
を1μm塗布しく第1図(C))、所定のパターンのフ
ォトマスクを用いて露光し、ケイ酸ソーダ溶液を用いて
フォトレジスト4と平坦化したポリイミド樹脂層3′を
同時に現像エツチングする(第1図(d))。
After that, photoresist 4 was heated at 135°C for 30 minutes.
The photoresist 4 and the flattened polyimide resin layer 3' are simultaneously developed and etched using a sodium silicate solution (Fig. 1(C)), and exposed using a photomask with a predetermined pattern. Figure 1 (d)).

そしてフォトレジスト4を剥離した後350°Cで1時
間加熱しポリイミド樹脂を完全に硬化させ、スルーホー
ル5′を形成した(第1図(e))。
After the photoresist 4 was peeled off, the polyimide resin was heated at 350° C. for 1 hour to completely cure the polyimide resin, thereby forming a through hole 5' (FIG. 1(e)).

さらにこの基板1上に第2配線層としてアルミニウム層
を蒸着し、フォトリソエツチングにより所定のパターン
を形成し、第2配線層5を形成した(第1図(f))。
Furthermore, an aluminum layer was deposited as a second wiring layer on this substrate 1, and a predetermined pattern was formed by photolithography to form a second wiring layer 5 (FIG. 1(f)).

ポリイミド樹脂N3を被覆後、紫外線照射してからバタ
ーニングしたサンプル〈第1図(e)の状態の基板)と
、従来法で形成した紫外線を照射しなかったサンプル(
第3図(d))の状態の基板)についてその膜厚、コー
テイング後の表面状態、エツチング後のスルーホール形
状について比較したものを第1表に示す。なお膜厚の測
定には触肚式膜厚測定計を用いた。
A sample was coated with polyimide resin N3, irradiated with ultraviolet rays, and then buttered (substrate in the state shown in Figure 1(e)), and a sample formed by the conventional method but not irradiated with ultraviolet rays (
Table 1 shows a comparison of the film thickness, surface condition after coating, and through hole shape after etching for the substrate in the state shown in FIG. 3(d)). Note that a palpable film thickness meter was used to measure the film thickness.

第1表 この表からも明らかなように紫外線照射を施こすことに
より被覆したポリイミド樹脂が平坦化しまたスルーホー
ル形成のためのエツチングによるバラツキもなくなった
Table 1 As is clear from this table, the coated polyimide resin was flattened by ultraviolet irradiation, and the variations caused by etching for forming through holes were also eliminated.

さらにアルミニウムから成る第2配線層5を形成したサ
ンプル(第1図(f)の状態の基板)についてのポリイ
ミド樹脂層と配線層との密着力テスト、絶縁性テストを
行ったが、アルミニウムとポリイミド、ポリイミドとク
ロムとの密着力、各配線層間の絶縁性とも問題がなかっ
た。
Furthermore, we conducted an adhesion test and an insulation test between the polyimide resin layer and the wiring layer on a sample (substrate in the state shown in FIG. 1(f)) on which the second wiring layer 5 made of aluminum was formed. There were no problems with the adhesion between polyimide and chromium, and the insulation between each wiring layer.

本発明により基板上に被覆されたポリイミド樹脂層が平
坦化され均一な膜となるのは、ポリイミド樹脂表面およ
び下層との界面に付着している活性分子がガス化し蒸発
して除去されるために両者のぬれが向上するとともに、
ポリイミド樹脂層の表面が平坦化し、その上履に被着す
る第2配線層とのぬれも向上するものと考えられる。
The reason why the polyimide resin layer coated on the substrate according to the present invention is flattened and becomes a uniform film is because the active molecules attached to the polyimide resin surface and the interface with the lower layer are gasified and evaporated and removed. As well as improving the wetness of both,
It is thought that the surface of the polyimide resin layer is flattened and its wettability with the second wiring layer adhered to the shoe is improved.

なお、本実施例では基板lとしてガラスを用いた例につ
いて説明したが本発明は混成集積回路基板として用いら
れるものであればこれに限られるものではなくセラミッ
ク等も用いることができる。
Although this embodiment describes an example in which glass is used as the substrate l, the present invention is not limited to this as long as it can be used as a hybrid integrated circuit board, and ceramics or the like can also be used.

同様に第一配線層としてはりbム、第二配線層としてア
ルミニウムを用いた例について説明したが、両者はそれ
ぞれアルミニウムや金でおきかえることもできる。
Similarly, an example has been described in which aluminum is used as the first wiring layer and aluminum is used as the second wiring layer, but both can be replaced with aluminum or gold, respectively.

〔発明の効果〕〔Effect of the invention〕

本発明によりポリイミド樹脂等有機物膜を被覆後紫外線
を一定時間照射するという比較的容易な工程を増すだけ
で中間絶縁層として平坦で均一な膜を得ることができ、
混成集積回路の高密度化、高信頼性、大面積化への対応
が可能な中間絶縁層を形成することができ、同時に多層
配線工程の簡略化、製造コストの低減を図ることができ
る。
According to the present invention, it is possible to obtain a flat and uniform film as an intermediate insulating layer by simply adding a relatively easy step of coating an organic film such as polyimide resin and irradiating it with ultraviolet rays for a certain period of time.
It is possible to form an intermediate insulating layer that is compatible with high density, high reliability, and large area hybrid integrated circuits, and at the same time, it is possible to simplify the multilayer wiring process and reduce manufacturing costs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の工程説明図、第2図はローラコーティ
ングの概略説明図、第3図は従来の工程説明図である。 1一基板      2−第1配線層 3−ポリイミド樹脂層 4−・フォトレジスト 5−・第2配線層5 ’ −−
−−スルーホール
FIG. 1 is a process explanatory diagram of the present invention, FIG. 2 is a schematic explanatory diagram of roller coating, and FIG. 3 is a conventional process explanatory diagram. 1 - Substrate 2 - First wiring layer 3 - Polyimide resin layer 4 - Photoresist 5 - Second wiring layer 5' --
--Through hole

Claims (1)

【特許請求の範囲】[Claims]  配線パターンを形成させた基板表面に中間絶縁層を設
けこの中間絶縁層上に配線パターンが形成され、この中
間絶縁層にポリイミド樹脂を用いた多層配線形成方法に
おいて、上記ポリイミド樹脂を被覆した後、紫外線を照
射してポリイミド樹脂の平坦化を行うことを特徴とする
多層配線形成方法。
In a multilayer wiring forming method in which an intermediate insulating layer is provided on the surface of a substrate on which a wiring pattern is formed, a wiring pattern is formed on this intermediate insulating layer, and a polyimide resin is used for this intermediate insulating layer, after coating with the polyimide resin, A multilayer wiring forming method characterized by flattening polyimide resin by irradiating ultraviolet rays.
JP23575686A 1986-10-03 1986-10-03 Method of forming multilayer interconnection Pending JPS6390893A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23575686A JPS6390893A (en) 1986-10-03 1986-10-03 Method of forming multilayer interconnection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23575686A JPS6390893A (en) 1986-10-03 1986-10-03 Method of forming multilayer interconnection

Publications (1)

Publication Number Publication Date
JPS6390893A true JPS6390893A (en) 1988-04-21

Family

ID=16990766

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23575686A Pending JPS6390893A (en) 1986-10-03 1986-10-03 Method of forming multilayer interconnection

Country Status (1)

Country Link
JP (1) JPS6390893A (en)

Similar Documents

Publication Publication Date Title
US5277749A (en) Methods and apparatus for relieving stress and resisting stencil delamination when performing lift-off processes that utilize high stress metals and/or multiple evaporation steps
JPH0537158A (en) Via hole structure and formation thereof
JPH05502138A (en) Interconnects in multilayer wiring and methods of forming them
JPS6390893A (en) Method of forming multilayer interconnection
JP2000216522A (en) Flexible board and manufacture thereof
JP3983077B2 (en) Probe substrate and manufacturing method thereof
JPH0537151A (en) Formation of thin film multilayer circuit
JP3215542B2 (en) Method of manufacturing multilayer thin film wiring board
JP3495272B2 (en) Lithographic method and wiring substrate manufacturing method
JP2001177253A (en) Manufacturing method for multilayer printed board
JP2644847B2 (en) Multilayer wiring board and method of manufacturing the same
JP3309584B2 (en) Method for manufacturing semiconductor device
JPS58191490A (en) Method of forming resist pattern
JPH03108798A (en) Multilayer wiring board and manufacture thereof
JPH09139564A (en) Thick film wiring and its formation
JPS59213131A (en) Manufacture of x-ray exposing mask
JPH05299845A (en) Manufacture of multilayered thin-film circuit board
JPH06244553A (en) Manufacture of thin film multilayered wiring board
JPS62165651A (en) Formation of resist pattern
JP3223598B2 (en) Multilayer wiring structure and method of forming multilayer wiring structure
JP2000040692A (en) Pattern formation method
JPH05299846A (en) Manufacture of wiring board
JPH06318774A (en) Manufacturing method of printed-wiring board
JPH05188589A (en) Photosensitive resist film and production of printed circuit board formed by using the same
JPH0737782A (en) Manufacture of organic thin film