JPS6390862U - - Google Patents
Info
- Publication number
- JPS6390862U JPS6390862U JP18582586U JP18582586U JPS6390862U JP S6390862 U JPS6390862 U JP S6390862U JP 18582586 U JP18582586 U JP 18582586U JP 18582586 U JP18582586 U JP 18582586U JP S6390862 U JPS6390862 U JP S6390862U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit device
- insulating tape
- resistant insulating
- planted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18582586U JPS6390862U (sk) | 1986-12-01 | 1986-12-01 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18582586U JPS6390862U (sk) | 1986-12-01 | 1986-12-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6390862U true JPS6390862U (sk) | 1988-06-13 |
Family
ID=31134815
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18582586U Pending JPS6390862U (sk) | 1986-12-01 | 1986-12-01 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6390862U (sk) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55121672A (en) * | 1979-03-13 | 1980-09-18 | Mitsubishi Electric Corp | Semiconductor device |
JPS57184239A (en) * | 1981-05-08 | 1982-11-12 | Nec Corp | Substrate for semiconductor device |
JPS59228739A (ja) * | 1983-06-10 | 1984-12-22 | Hitachi Ltd | 半導体装置 |
-
1986
- 1986-12-01 JP JP18582586U patent/JPS6390862U/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55121672A (en) * | 1979-03-13 | 1980-09-18 | Mitsubishi Electric Corp | Semiconductor device |
JPS57184239A (en) * | 1981-05-08 | 1982-11-12 | Nec Corp | Substrate for semiconductor device |
JPS59228739A (ja) * | 1983-06-10 | 1984-12-22 | Hitachi Ltd | 半導体装置 |