JPS6390844U - - Google Patents
Info
- Publication number
- JPS6390844U JPS6390844U JP18746986U JP18746986U JPS6390844U JP S6390844 U JPS6390844 U JP S6390844U JP 18746986 U JP18746986 U JP 18746986U JP 18746986 U JP18746986 U JP 18746986U JP S6390844 U JPS6390844 U JP S6390844U
- Authority
- JP
- Japan
- Prior art keywords
- unit
- semiconductor integrated
- integrated circuit
- circuit device
- logic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Description
第１図は本考案の一実施例を説明する為の遅延
回路の構成図、第２図は従来の半導体集積回路装
置の平面図、第３図は本考案の一実施例における
抵抗の平面図、第４図は本考案の一実施例におけ
る抵抗及び容量素子の平面図である。
１…チツプ、２…入出力バツフア回路セル、３
…基本セル、１１…インバータ、１２…抵抗、１
３…容量素子、２１，２２…基本セル列、３１…
配線領域、４１…拡散抵抗、５１…ポリシリコン
抵抗、６１…容量素子。
Fig. 1 is a block diagram of a delay circuit for explaining an embodiment of the present invention, Fig. 2 is a plan view of a conventional semiconductor integrated circuit device, and Fig. 3 is a plan view of a resistor in an embodiment of the present invention. , FIG. 4 is a plan view of a resistive and capacitive element in an embodiment of the present invention. 1... Chip, 2... Input/output buffer circuit cell, 3
...Basic cell, 11...Inverter, 12...Resistor, 1
3... Capacitive element, 21, 22... Basic cell row, 31...
Wiring region, 41... Diffused resistor, 51... Polysilicon resistor, 61... Capacitive element.
Claims (1)
素子をアレイ状にくりかえして配置したマスター
スライスに配線をして論理回路を構成して成る半
導体集積回路装置において、前記単位素子列間の
配線領域に受動素子を形成し、前記単位素子と遅
延回路を構成したことを特徴とする半導体集積回
路装置。 In a semiconductor integrated circuit device in which a logic circuit is formed by wiring a master slice in which unit elements forming a logic circuit are repeatedly arranged in an array on a main surface of a semiconductor substrate, a wiring area between the rows of unit elements. A semiconductor integrated circuit device comprising a passive element formed in the unit element and a delay circuit formed with the unit element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18746986U JPS6390844U (en) | 1986-12-04 | 1986-12-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18746986U JPS6390844U (en) | 1986-12-04 | 1986-12-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6390844U true JPS6390844U (en) | 1988-06-13 |
Family
ID=31137978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18746986U Pending JPS6390844U (en) | 1986-12-04 | 1986-12-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6390844U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0316173A (en) * | 1989-06-14 | 1991-01-24 | Fujitsu Ltd | Semicustom integrated circuit device |
-
1986
- 1986-12-04 JP JP18746986U patent/JPS6390844U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0316173A (en) * | 1989-06-14 | 1991-01-24 | Fujitsu Ltd | Semicustom integrated circuit device |
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