JPS6390207A - Clock signal generating circuit for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To increase the operation speed by not raising the level of an output signal with one buffer circuit but raising the level of the output signal stepwise with plural buffer circuits to shorten the rise time of the level of the output signal even in case of the use of a voltage source, whose output resistance is relatively high, in the last output stage. CONSTITUTION:When a set signal S0 goes to a high level at a time t1, a buffer circuit B1 is operated to quickly raise an output voltage OT1 up to an about potential V1 of a voltage source 2 at a time t2 after a rise time T1. If a following set signal S1 is set to the high level at a time t3 when the output signal OT1 sufficiently approaches the level V1, the operation of the buffer circuit B1 is stopped and an output terminal (d) of the buffer circuit B1 is brought to the floating state. Meanwhile, the operation of a buffer circuit B2 is started simultaneously to raise the output signal OT1 from the level V1 to a voltage V0 of a voltage source 1 at a time t4. Since the output resistance of the voltage source 1 which gives the output level of the buffer circuit B2 is high, a rise time T2 is longer than the rise time T1. Thus, a time t01 is shortened to be equal to the time T1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock signal generation circuit for a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit in which the output level of a voltage source whose output resistance is relatively high is set to the high level of a clock signal. The present invention relates to a circuit clock signal generation circuit.

[Conventional technology]

As a conventional dynamic type clock signal generation circuit for semiconductor integrated circuits, there is one shown in FIG. The clock signal generation circuit for a semiconductor integrated circuit shown in FIG.
The circuit published in I S S CC Digest (ISS CCdigest) 1980, pages 230 and 231 by John Y.
John Y. Chan et al.
IEEE Journal of Solid State Circuits
Lid-State Circuits) Volume 5C-15, No. 5, lθ, 1980.

This is a slightly modified and simplified version of the circuit presented on pages 839-846.

FIG. 4 is a waveform diagram for explaining the operation of the semiconductor integrated circuit clock signal generation circuit of FIG. 3.

The operation of the clock signal generation circuit for a semiconductor integrated circuit shown in FIG. 3 will be explained below with reference to FIG. 4. Note that in the following explanation, an N-channel MOSFET is used as the MISFET.
Assume that SFET is used.

In FIG. 3, during standby, the reset signal R applied to the input terminals S and C is at a high level, so that the node N is activated. ,
N2 is precharged to a low level (OV), and node N1 is precharged to a high level. Furthermore, the set signal So applied to the input terminal a is at a low level, and the MO3FETQo, Ql, 0
i is in a conductive state, and MOSFETQ2 is in a non-conductive state. Therefore, the output signal OT on the output terminal d is fixed at a low level. This state is dynamically maintained even if the reset signal R becomes low level.

Next, when the set signal SO becomes high level, MOS F
Node N2 begins to charge to a high level through E T Q o. However, when the set signal So becomes high level,
Node N. becomes high level, so that node N, becomes low level, and at the same time MO3FET Qo becomes non-conductive. At this point, charging of node N2 through MO3FETQo ends, but at the same time, the level of node N2 is boosted to a higher level due to coupling via boost capacitor C, and the level of node N2 is boosted to a higher level to fully charge MOSFET Q2 in the output stage. Make it conductive. This MOS FET Q2 charges the output terminal d and pulls the output signal OT to a high level. The high level of the output signal OTo at this time is equal to the potential ■o of the voltage source 1 connected to the power supply terminal e (drain of MOS FET Q2).

However, if the output (internal) resistance of voltage source 1 is high,
As shown by the solid line in FIG. 4, the rise time To of the output signal OTo increases (the broken line in FIG. 4 shows the signal waveform when the output resistance of the voltage source 1 is low).

In recent years, semiconductor integrated circuits such as large-capacity dynamic RAMs often mount a power supply voltage conversion circuit on the chip to convert an external power supply voltage to a voltage for internal use. It is possible to reduce the output resistance of such an on-chip voltage conversion circuit by optimizing the size of the MOSFET used, but considering the practical size and power consumption, it is not possible to increase the size of the MOSFET too much. As a result, it has a relatively high output resistance.

[Problem that the invention seeks to solve]

The conventional clock signal generation circuit for semiconductor integrated circuits described above uses the output of an on-chip voltage conversion circuit with a relatively high output resistance at a high level, so there is a serious problem that the rise time of the clock signal becomes extremely long. There are some drawbacks.

An object of the present invention is to provide a semiconductor integrated circuit in which, even if the output resistance of an on-chip voltage conversion circuit is relatively high, the rise of a clock signal generated using the output of the on-chip voltage conversion circuit is faster than that of a conventional circuit. An object of the present invention is to provide a clock signal generation circuit for a circuit.

[Means for solving problems]

The clock signal generation circuit for semiconductor integrated circuits of the present invention includes:
The respective output terminals, which can be in a floating state and each output a different output voltage, are commonly connected, and the operation is transitioned from a low output voltage to a high output voltage, and the output is output from any one circuit of the output terminals. It has a plurality of buffer circuits that keep the other output terminals in a floating state while a voltage is being output.

[Effect]

The clock signal generation circuit for semiconductor integrated circuits of the present invention has a low output level but a strong load driving ability, that is, a low output resistance, and uses a buffer circuit to rapidly raise its output (clock signal) to an appropriate intermediate level. After that, by sequentially driving a bus circuit with a high output level but a relatively weak load driving ability, that is, a high output resistance, up to the required final level, a clock signal with a high level and a short rise time is generated. is occurring.

(Examples) Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

As shown in FIG. 1, this embodiment has two buffer circuits B.
,,B, and a voltage source 1.2.

FIG. 2 is a waveform diagram for explaining the operation of the embodiment shown in FIG.

The operation of the embodiment shown in FIG. 1 will be explained below with reference to FIG. 2.

In FIG. 1, the circuit structure of buffer circuits B, B2 is the same as that of the clock signal generation circuit for semiconductor integrated circuit shown in FIG. 3 described above. However, it is assumed that the voltage source 2 of the buffer circuit B has a low output resistance, and the voltage source 1 of the buffer circuit B2 has a high output resistance.

This operation is performed by first changing the reset signal R from a high level to a low level to preset each node of the buffer circuits B, B2 to an initial state, and then sequentially inputting the set signals So and S.

That is, the time 1 shown in FIG. When the set signal So becomes high level, the buffer circuit B1 operates and the rise time T
At time t2 after I has elapsed, the output signal OT is rapidly raised to near the potential V1 of the voltage source 2.

Furthermore, the output signal OT has sufficiently approached the ■l level.
Time 1 shown in Figure 2. Time t3 after time to1 has elapsed since
Then, the next set signal S1 is set to high level. As a result, the operation of the buffer circuit B is stopped, and the operation of the buffer circuit B is stopped.
, the output terminal d of is in a floating state.

On the other hand, at the same time, the operation of buffer circuit B2 becomes more and more
At time t4 after a rise time T2 has elapsed from time t3 shown in FIG. 2, the output signal OT is raised from the level ■l to the voltage ■o of the voltage source 1. However, since the output resistance of the voltage source l that provides the output level of the buffer circuit B2 is high, the rise time T2 is longer than the rise time T1.

Although the operation is completed by the above procedure, the rise time T12 of the output signal OT1 shown in FIG. As a result, Tl+
It is possible to shorten it to T2.

According to this embodiment, as shown in FIG. 4 described above, only one buffer circuit is required. The output signal OT
The time it takes for the level of , to rise from the low level to the ■l level (corresponding to T in Figure 2) can be significantly shortened,
As a result, the rise time to the Vg level can be significantly shortened (1゛1□<T,).

For convenience, all the above explanations are based on N-channel MOSFETs.
Although the example uses an ET, the present invention is essentially equally applicable to a P-channel MOSFET or any other type of transistor.

Further, the number of buffer circuits is not limited to two, and the present invention can be similarly applied even if a plurality of buffer circuits are used.

〔Effect of the invention〕

As explained above, the clock signal generation circuit for semiconductor integrated circuits of the present invention uses a plurality of buffer circuits to raise the level of the output signal stepwise, instead of raising the level of the output signal with one buffer circuit. By raising the output voltage, the rise time of the level of the output signal can be shortened even when a voltage source with a relatively high output resistance is used in the final output stage, so there is an effect that the speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the embodiment of FIG. 1, and FIG. 3 is a diagram of a conventional clock signal generation circuit for semiconductor integrated circuits. An example circuit diagram, FIG. 4, is a waveform diagram for explaining the operation of the clock signal generation circuit for a semiconductor integrated circuit shown in FIG. 3. 1.2... Voltage source, B, , B2... Buffer circuit,
OTo, OT,... Output signal, R... Signal to reset 1, So. +1 Iwa I V δo, St: T-Ntoi divination No. 2 Sonogyu 3 Figure No. 4 @

Claims (1)

[Claims] The respective output terminals, which can be in a floating state and each output a different output voltage, are commonly connected, and the operation is transitioned from a low output voltage to a high output voltage, and the output is output from any one circuit of the output terminals. A clock signal generation circuit for a semiconductor integrated circuit, comprising a plurality of buffer circuits that keep other output terminals in a floating state while a voltage is being output.