JPS6390137A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6390137A
JPS6390137A JP23460486A JP23460486A JPS6390137A JP S6390137 A JPS6390137 A JP S6390137A JP 23460486 A JP23460486 A JP 23460486A JP 23460486 A JP23460486 A JP 23460486A JP S6390137 A JPS6390137 A JP S6390137A
Authority
JP
Japan
Prior art keywords
deposited
hexadecane
resist
contact angle
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23460486A
Other languages
Japanese (ja)
Inventor
Yasuo Wada
恭雄 和田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP23460486A priority Critical patent/JPS6390137A/en
Publication of JPS6390137A publication Critical patent/JPS6390137A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To obtain a highly reliable multilayer interconnection by a method wherein a low-energy surface whose contact angle in relation to n-hexadecane is partially more than 100 deg. is formed on the surface of a semiconductor device and an insulating material is deposited by a CVD method at a part other than that part. CONSTITUTION:An n-ch MOSFET is formed on a p-type Si substrate 21, and an Al wiring 26 is formed by making use of photoresist 27 as a mask. If the photoresist 27 is covered with a fluoride film by being exposed to an F plasma and CVD SiO2 28 is deposited at 100 deg. by pouring SiH4 and N2O, the SiO2 remains deposited selectively on PSG 25 only. If the resist 27 is removed after that, a flat interlayer insulating-film 29 can be formed by an ordinary CVO method. As a result, a multilayer interconnection of high reliability can be obtained. Because, at the fluoridized resist 27, the surface energy is small and the adsorption probability of the SiH4 is small, the SiO2 is not deposited. The contact angle in relation to n-hexadecane as an index for the surface energy corresponds well to the adsorption probability of the SiH4, it is preferable to select a fluoridized resist surface whose contact angle in relation to the n-hexadecane is more than 100 deg..

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置(IC)の¥!5造方決方
法し、さらに詳述すればICの平坦、かつ高信頼性多層
配線形成方法に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to semiconductor integrated circuit devices (IC). 5, and more specifically, it relates to a method for forming IC flat and highly reliable multilayer wiring.

〔従来の技術〕[Conventional technology]

近年のICにおける高性能多層配線技術は、例えばバイ
アス・スパッタ法により形成された非常に平坦な5iO
z膜を、層間の絶縁膜として使用する必要が生じて来た
。この理由は、ICの高密度化に伴ない、素子表面の凹
凸が横方向寸法に比べて無視出来なくなり、その結果段
差部の影響によるステップカバレージ不良の生ずる可能
性が大きくなって来たため、段差端部での配線不良の原
因となって来たからである。
In recent years, high-performance multilayer interconnection technology in ICs has developed, for example, using extremely flat 5iO formed by bias sputtering.
It has become necessary to use Z films as interlayer insulating films. The reason for this is that as the density of ICs increases, the unevenness on the element surface cannot be ignored compared to the lateral dimension, and as a result, the possibility of poor step coverage due to the influence of the stepped portion increases. This is because it has become a cause of wiring defects at the ends.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

すなおち従来技術では、第2図に示すように、例えば半
導体基板11上に形成した絶縁膜12を介して第1の導
電体13を形成した状態で、化学蒸着法(以下CVD法
と略)により層間絶縁14を堆積し、さらに第2の導電
体15を形成した状態である。該第1の導電体13の線
間間隔が狭くなるに従がい、該層間絶縁膜14の膜厚が
場所により均一でなくなり、特に該第1の導電体の間の
凹部への該絶縁膜14の堆積膜厚は極端に薄くなる。そ
の結果、第1の導電体と第2の導電体の間に短絡が生じ
たり、あるいは第2の導電体15に断線が生ずる。
In other words, in the conventional technology, as shown in FIG. 2, for example, a first conductor 13 is formed on a semiconductor substrate 11 through an insulating film 12, and then a chemical vapor deposition method (hereinafter abbreviated as CVD method) is used. In this state, an interlayer insulation 14 is deposited and a second conductor 15 is further formed. As the distance between the lines of the first conductors 13 becomes narrower, the thickness of the interlayer insulating film 14 becomes uneven depending on the location, and in particular, the thickness of the interlayer insulating film 14 becomes uneven in the recesses between the first conductors. The deposited film thickness becomes extremely thin. As a result, a short circuit occurs between the first conductor and the second conductor, or a break occurs in the second conductor 15.

このような多層配線の不良を防止するために考案された
のが、バイアス・スパッタ技術による層間絶縁膜の形成
法である。半導体基板11上に絶縁膜12を介して形成
した第1の導電体13上に、バイアス・スパッタ法によ
り形成した層間膜16を堆積する事により、平坦な表面
が得られ、その結果第2の4電体15は、断線、短絡等
の不良を起さずに形成される。しかしながらこのバイア
ススパッタ法では、(1)荷電ビームで衝撃を与える為
既に形成されているデバイスに損傷を与える。
A method of forming an interlayer insulating film using bias sputtering technology has been devised to prevent such defects in multilayer wiring. By depositing the interlayer film 16 formed by bias sputtering on the first conductor 13 formed on the semiconductor substrate 11 via the insulating film 12, a flat surface is obtained, and as a result, the second conductor 13 The four electric bodies 15 are formed without causing defects such as disconnections and short circuits. However, in this bias sputtering method, (1) an impact is applied with a charged beam, which damages already formed devices.

(2)スパッタエッチを行ないながら堆積する為、膜堆
積速度が極端に遅い、(3)ある程度以上幅の広いパタ
ーンの上には、原理的に、元の段差より大きな段差が形
成される、等の問題があり、必ずしも実用化されていな
い。
(2) Since the film is deposited while performing sputter etching, the film deposition rate is extremely slow. (3) In principle, a step larger than the original step is formed on a pattern that is wider than a certain level. There are problems with this, and it has not always been put into practical use.

従来技術の問題点をもう一度要約すると、第一の導電体
の段差に起因する層間絶縁膜及び第二の導電体層の不良
現象のため、高密度ICにおける多層配線は非常に困難
であり、該第−の導電体の段差の影響を有効に緩和する
事が必要である。
To summarize the problems of the prior art once again, multilayer wiring in high-density ICs is extremely difficult due to defects in the interlayer insulating film and the second conductor layer caused by the step difference in the first conductor. It is necessary to effectively alleviate the influence of the step difference in the second conductor.

本発明の目的はこのような従来技術の問題点を解決する
ために、該第−の導電体に起因する段差と自己整合的に
該層間絶縁膜で低減する技術を開示する事である。
An object of the present invention is to disclose a technique for reducing the level difference caused by the second conductor by using the interlayer insulating film in a self-aligned manner in order to solve the problems of the prior art.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的を達成する為に本発明では第一の導電体の周隙
部に選択的に層間絶縁膜を形成し、該第−の導電体によ
り形成された段差を実効的に除去する事を骨子とする6
層間絶縁膜の選択形成のためには、該第−の導電体表面
には堆積せず、第一の導電体の間隙部のみに堆積が行な
われる化学蒸着法(以下CVD法)を用いればよい。
In order to achieve the above object, the present invention aims to selectively form an interlayer insulating film in the periphery of the first conductor to effectively remove the step formed by the second conductor. 6
In order to selectively form the interlayer insulating film, it is sufficient to use a chemical vapor deposition method (hereinafter referred to as CVD method) in which the interlayer insulating film is not deposited on the surface of the second conductor but is deposited only in the gap of the first conductor. .

〔作用〕[Effect]

本発明の原理を第1図を用いて説明する。シリコン基板
1上に絶縁膜2を介して形成された第一の導電体3上に
存在する有機物p?J4を有する本町造において、モノ
シラン(SiHa)および亜酸化窒素(NzO)を用い
たCVDによるSiO2の堆積を行なうと、該有機物層
4上には何も堆積せず、該絶縁膜2上には5iOz5の
堆積が起る。
The principle of the present invention will be explained using FIG. The organic substance p? present on the first conductor 3 formed on the silicon substrate 1 via the insulating film 2? When depositing SiO2 by CVD using monosilane (SiHa) and nitrous oxide (NzO) in Honmachi-zukuri with J4, nothing is deposited on the organic layer 4 and nothing is deposited on the insulating film 2. Deposition of 5iOz5 occurs.

該第−の導電体3とほぼ同程度の膜厚迄該5iOzを堆
積させた後、該有機物層4を除去し、さらに通常のCV
D法によりさらに絶縁物を堆積する事により、平坦な層
間絶縁膜が形成出来、その結果、信頼性の高い多層配線
構造を形成出来る。該有機物層の存在は必ずしも必須で
はなく、該CVDにより堆積される5i025の選択反
応が起るだけ十分に表面状態が該第−の導電体3上と絶
縁膜2上とで差異が有ればよい。この表面状態の差異に
より、該5iOz5が堆積される部分と堆積されない部
分が存在する事になる。一般的に表面エネルギが十分小
さく、CVDを行なう時にガスの吸着が起らないように
する事により堆積を防止可能である。
After depositing the 5iOz to a film thickness almost the same as that of the second conductor 3, the organic layer 4 is removed, and then a normal CV
By further depositing an insulator using the D method, a flat interlayer insulating film can be formed, and as a result, a highly reliable multilayer wiring structure can be formed. The presence of the organic material layer is not necessarily essential, as long as the surface conditions on the second conductor 3 and the insulating film 2 are sufficiently different to cause a selective reaction of 5i025 deposited by the CVD. good. Due to this difference in surface condition, there are parts where the 5iOz5 is deposited and parts where it is not. In general, the surface energy is sufficiently small and deposition can be prevented by preventing gas adsorption during CVD.

〔実施例〕〔Example〕

以下本発明を実施例に基づき詳細に説明する。 The present invention will be described in detail below based on examples.

実施例1 本実施例では該第−の導電体表面に形成された有機物の
表面を弗素プラズマにより弗化し、表面エネルギを小さ
くする事により、該絶縁膜」;に選択的に層間絶縁膜を
形成する方法を開示する。
Example 1 In this example, an interlayer insulating film was selectively formed on the insulating film by fluorinating the surface of the organic material formed on the surface of the second conductor with fluorine plasma to reduce the surface energy. Disclose a method to do so.

第4図(a)はP型(100)面1oΩ”dllのシリ
コン基板21上に通常のn−チャネルMOSプロセス(
以下n−MOSプロセス)により、厚さ0.8  μm
の熱酸化により成長させた素子分離酸化膜22、厚さ2
0nmのゲート酸化膜20CVD法で堆積したpaly
 −S iゲート23、ヒ素のイオン打込みにより形成
したソース・ドレーン領域24.CVI)法で堆積した
リンガラス(psG)膜25を形成し、さらにAQ!!
j!線26をホ上26スト27をマスクにして加工した
状態を示す。
FIG. 4(a) shows a conventional n-channel MOS process (
Thickness: 0.8 μm by n-MOS process)
Element isolation oxide film 22 grown by thermal oxidation, thickness 2
0nm gate oxide film 20Paly deposited by CVD method
-Si gate 23, source/drain regions 24 formed by arsenic ion implantation. A phosphorus glass (psG) film 25 is formed using the AQ! !
j! A state in which the line 26 is processed using the upper 26 stroke 27 as a mask is shown.

第4図(b)は該構造を弗素プラズマ中に曝し。FIG. 4(b) shows the structure exposed to fluorine plasma.

該ホトレジスト27表面に弗化膜を形成後、S i 1
14とNxOガスを流したC V D炉中に入れ、基板
温度を100℃迄昇温し、SiOx層28を堆積した状
態を示す。この時、該レジスト27の表面には5iHa
が吸着さねない為、該P S G 25表面上にのみ5
iOz28が堆積される。該5iOz28がプラズマ弗
化したレジスト27上に形成されない理由は、該弗化し
たレジスト27上へのモノシランの吸着が無く、従って
SiOxの形成反応が起らない為である。即ち、表面エ
ネルギが小さいと、気体の吸着確率が小さくなる。第5
図に示したように、表面エネルギの指標であるノルマル
ヘキサデカン(n −hexadacar 、以下n−
ヘキサデカン)に対する接触角と、モノシランの吸着確
率は、よい対応を示しており、n−ヘキサデカンの接触
角が100度以上になると1選択成長が可能になる8度
の選択吸着性を示すようになる事が分かる。従って、選
択成長が起るようにするには少なくとも試料表面の表面
エネルギをnヘキサデカンに対する接触角で100度以
上にする事が必要である。第4図(C)は、該レジスト
27を酸素プラズマにより除去後、さらにCVD法によ
り5iOz層29を堆積、第2の導電体JW30を形成
した状態を示す。
After forming a fluoride film on the surface of the photoresist 27, S i 1
The substrate was placed in a CVD furnace through which NxO gas was flowed, the substrate temperature was raised to 100°C, and a SiOx layer 28 was deposited. At this time, the surface of the resist 27 has 5iHa.
5 only on the surface of the PSG 25 because it will not be adsorbed.
iOz28 is deposited. The reason why the 5iOz 28 is not formed on the plasma fluorinated resist 27 is that monosilane is not adsorbed onto the fluorinated resist 27, and therefore no SiOx formation reaction occurs. That is, when the surface energy is small, the probability of gas adsorption becomes small. Fifth
As shown in the figure, normal hexadecane (n-hexadacar, hereinafter n-hexadacar) is an indicator of surface energy.
The contact angle for n-hexadecane (hexadecane) and the adsorption probability of monosilane show a good correspondence, and when the contact angle of n-hexadecane becomes 100 degrees or more, it shows a selective adsorption of 8 degrees, which enables one-selective growth. I understand. Therefore, in order to cause selective growth, it is necessary to make the surface energy of the sample surface at least 100 degrees or more at the contact angle with respect to n-hexadecane. FIG. 4C shows a state in which after the resist 27 is removed by oxygen plasma, a 5iOz layer 29 is further deposited by CVD to form a second conductor JW30.

基板温度は、該有機材料として用いたレジスト27の耐
熱性と1反応の選択性によって選ぶ事が出来る。例えば
ポリイミド系の有機材料を用いれば、基板温度は400
℃程度迄上昇させる事が可能であるが、表面の弗化物が
分解1反応の選択性が低下する為、350℃程度以下が
適切な温度である。又温度が500℃以上に高くなると
、5iHaが気相で分解し、表面反応の選択性が小さく
なる為本発明の骨子である絶縁膜の選択成長は出来なく
なる。
The substrate temperature can be selected depending on the heat resistance of the resist 27 used as the organic material and the selectivity of one reaction. For example, if a polyimide-based organic material is used, the substrate temperature will be 400°C.
Although it is possible to raise the temperature to about 350°C, the appropriate temperature is about 350°C or lower because fluoride on the surface reduces the selectivity of the decomposition 1 reaction. Furthermore, when the temperature rises to 500° C. or higher, 5iHa decomposes in the gas phase, and the selectivity of the surface reaction decreases, making it impossible to selectively grow an insulating film, which is the gist of the present invention.

反応ガスは1本発明では5iHaとN z Oの混合ガ
スを用いたが、反応の選択性を向上させる為には、表面
吸着の起り易いガスを選ぶ事が出来る。
In the present invention, a mixed gas of 5iHa and N z O was used as the reaction gas, but in order to improve the selectivity of the reaction, a gas that is likely to be adsorbed on the surface can be selected.

例えば、ジクロルシラン(S i HxCQz) 、ク
ロルシラン(Si)(gcffi)とNzO等の混合ガ
スは、選択性を上げるが、ジシラン(S i zHe)
等の化合物は、分解して5iHa  ・というラジカル
を形成し易く、反応性が高い為1選択的な堆積は困難に
なる。又酸化剤として純粋酸素を用いると、やはり反応
性が高(S i Oxを形成し易い為、選択性は小さく
なり、反応ガスとしては不適当である。
For example, mixed gases such as dichlorosilane (S i HxCQz), chlorosilane (Si) (gcffi) and NzO increase selectivity, but disilane (S i zHe)
These compounds tend to decompose to form radicals such as 5iHa 2 and have high reactivity, making selective deposition difficult. Further, when pure oxygen is used as an oxidizing agent, the reactivity is high (SiOx is easily formed), so the selectivity is low, and it is unsuitable as a reaction gas.

紫外線の照射による選択堆積も可能である。この場合に
は、例えば塩化キセノン(XeCQ)を用いた波長3Q
8nmのエキシマレーザ、あるいはアルゴンレーザ等の
レーザ光の使用でも、あるいはキセノンランプ、水銀ラ
ンプ等の多波長光源でも効果はある。表面に吸着したガ
スを光で励起し1選択的に5iftを形成させる事が可
能である。この場合にも、表面エネルギの大きさはn 
−ヘキサデカンに対する接触角で100度以下が適切で
ある。
Selective deposition by irradiation with ultraviolet light is also possible. In this case, for example, wavelength 3Q using xenon chloride (XeCQ)
It is also effective to use a laser beam such as an 8 nm excimer laser or an argon laser, or a multi-wavelength light source such as a xenon lamp or a mercury lamp. It is possible to selectively form 5ift by exciting the gas adsorbed on the surface with light. In this case as well, the magnitude of the surface energy is n
- A suitable contact angle for hexadecane is 100 degrees or less.

実施例2 本実施例では表面処理により表面エネルギの小さい状態
を作り、選択堆積を可能にする方法について開示する。
Example 2 This example discloses a method of creating a state of low surface energy through surface treatment to enable selective deposition.

第6図(a)はP型(100)面10Ω・国のシリコン
基板21上に熱酸化により成長させた熱酸化膜22.第
1の導電体層26を形成後、弗素ガス雰囲気中でプラズ
マを照射し、該熱酸化膜上にシリコン弗化物M!J31
、およびアルミニウム配線26上にアルミニウム弗化物
層32をおのおの形成した状態を示す。
FIG. 6(a) shows a thermal oxide film 22 grown by thermal oxidation on a P-type (100) 10Ω silicon substrate 21. After forming the first conductor layer 26, plasma is irradiated in a fluorine gas atmosphere to form silicon fluoride M! on the thermal oxide film. J31
, and a state in which an aluminum fluoride layer 32 is formed on the aluminum wiring 26, respectively.

第6図(b)は、このようにして形成した構造を約40
0℃に加熱し、該シリコン弗化物MJ31を蒸発させ、
該アルミニウム26上にのみ表面エネルギの小さいアル
ミニウム弗化物層32を残した後、5iHaとN x 
Oの混合ガス雰囲気中で基板温度を200℃に加熱しな
がら5iOz層28を堆積した状態を示す、この時該熱
酸化膜22上へは毎分1000人、又該アルミニウム弗
化物層32上へは毎分50人の堆積が起った。従がって
該第−の導電体)g126の膜厚を1μmとすれば、1
0分間5iOz層28を堆積すれば、はぼSjt垣な配
線構造を得る事が可能となる。さらに層間絶縁膜29を
必要な厚さ堆積し、第二の導電体層30を形成する事に
より、二層配線は完成する。
FIG. 6(b) shows the structure formed in this way at approximately 40 mm.
heating to 0° C. to evaporate the silicon fluoride MJ31;
After leaving the aluminum fluoride layer 32 with low surface energy only on the aluminum 26, 5iHa and N x
5iOz layer 28 is deposited while heating the substrate temperature to 200° C. in a mixed gas atmosphere of O. At this time, the thermal oxide film 22 is deposited at a rate of 1000 per minute, and the aluminum fluoride layer 32 is deposited at a rate of 1000 per minute. 50 people were deposited every minute. Therefore, if the film thickness of the -th conductor) g126 is 1 μm, then 1
By depositing the 5iOz layer 28 for 0 minutes, it is possible to obtain a wiring structure similar to that of Sjt. Further, by depositing an interlayer insulating film 29 to a required thickness and forming a second conductive layer 30, the two-layer wiring is completed.

三層以上の配線構造は、さらに絶a膜の選択CVD、絶
縁膜の堆積、配線の形成を繰り返す事により形成できる
。又、下層の導電体層へのコンタクト形成時に、アルゴ
ン(Ar)イオンによるスパッタ等を行ない、該下層の
導電体層表面に形成されているアルミニウム弗化物等の
不良導体層を除去する事が必要な事は言う迄もない。
A wiring structure of three or more layers can be formed by further repeating the selective CVD of an insulating film, the deposition of an insulating film, and the formation of wiring. Furthermore, when forming a contact to the lower conductive layer, it is necessary to perform sputtering using argon (Ar) ions to remove defective conductive layers such as aluminum fluoride formed on the surface of the lower conductive layer. Needless to say.

又選択絶縁膜の膜厚は、導電体層と同程度である事が、
段差の低減という面からは最適であるが厚膜が厚くなり
過ぎるとクラック、ストレス等の問題が生ずる為、1μ
m以上にする事は適当でなし4゜ 〔発明の効果〕 本発明によれば、はぼ完全な平坦多層配tl& ’、1
!l iNの形成が可能となり、断線、短絡等の問題点
をほぼ完全に防止できるばかりでなく、信頼性も大幅に
向上可能である為、技術的効果は大きい。
In addition, the thickness of the selective insulating film is approximately the same as that of the conductive layer.
Although it is optimal in terms of reducing the level difference, if the film becomes too thick, problems such as cracks and stress will occur, so 1μ
It is not appropriate to make it more than m.4゜[Effect of the invention] According to the present invention, a completely flat multilayer structure tl&', 1
! It is possible to form l iN, which not only can almost completely prevent problems such as disconnections and short circuits, but also greatly improves reliability, which has great technical effects.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理を示す図、第2図乃至第3図は従
来技術の説明図、第4図乃至第6図は。 本発明の実施例を示す図。 1.11.21・・・半導体基板、12,22.20・
・・絶縁膜、5,14,16,28.29・・・層間絶
第2図 第3n (I7) CC) 第5図 縛触内(屋り 猶l胆
FIG. 1 is a diagram showing the principle of the present invention, FIGS. 2 and 3 are explanatory diagrams of the prior art, and FIGS. 4 to 6 are diagrams illustrating the prior art. FIG. 1 is a diagram showing an example of the present invention. 1.11.21...Semiconductor substrate, 12,22.20.
... Insulating film, 5, 14, 16, 28. 29... Layer separation Figure 2 3n (I7) CC) Figure 5

Claims (1)

【特許請求の範囲】[Claims] 1、n−ヘキサデカンとの接触角が少なくとも100度
以上であるような表面エネルギの低い表面を半導体装置
の表面の一部に部分的に形成する工程と、化学蒸着法に
より該表面エネルギの低い部分以外に絶縁物を堆積する
工程を少なくとも含む事を特徴とする半導体装置の製造
方法。
1. A process of partially forming a surface with low surface energy such that the contact angle with n-hexadecane is at least 100 degrees or more on a part of the surface of the semiconductor device, and forming the part with low surface energy by chemical vapor deposition. 1. A method for manufacturing a semiconductor device, comprising at least the step of depositing an insulator.
JP23460486A 1986-10-03 1986-10-03 Manufacture of semiconductor device Pending JPS6390137A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23460486A JPS6390137A (en) 1986-10-03 1986-10-03 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23460486A JPS6390137A (en) 1986-10-03 1986-10-03 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6390137A true JPS6390137A (en) 1988-04-21

Family

ID=16973635

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23460486A Pending JPS6390137A (en) 1986-10-03 1986-10-03 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6390137A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0847082A2 (en) * 1996-12-04 1998-06-10 France Telecom Process of treating a semiconductor substrate comprising a surface treatment step

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0847082A2 (en) * 1996-12-04 1998-06-10 France Telecom Process of treating a semiconductor substrate comprising a surface treatment step
EP0847082A3 (en) * 1996-12-04 1998-07-22 France Telecom Process of treating a semiconductor substrate comprising a surface treatment step

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