JPS638961A - Data input circuit - Google Patents

Abstract

PURPOSE:To correctly input only the data to be inputted by providing a permitting circuit to input effectively only a pair of input data in continuation to a permitting signal supplying means and a permitting signal. CONSTITUTION:Onto a data bus 1, an address signal to designate either of the permitting data and a data register 7 and an input data signal are successively supplied from a microcomputer. Into a writing circuit 9, a status signal to synchronize so as to gate the permitting data and the address signal, and three writing signals to synchronize to the permitting data, the address signal and the input data signal are inputted. The writing circuit 9 generates two command writing signals to synchronize to the permitting data and the address signal and a data writing signal to synchronize to the data signal. A permitting circuit 3 latches the permitting data of the bus 1 with a writing signal and a command writing signal and supplies the permitting signal to a selector 5. The selector 5 latches the address signal with the permitting signal and the command writing signal and generates the selecting signal to the data register 7.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a data input circuit, and more particularly, to a data input circuit that controls data input so that only data to be input can be input accurately without errors. Regarding circuits.

(Prior art) For example, when data supplied from a microcomputer etc. via a data bus is inputted via a data register, the input data is usually supplied together with a write signal, and the input data is gated by this write signal. Latched in data register.

In addition, when there are multiple data registers, an address signal for selecting a data register is supplied prior to input data in order to determine which data register to input data through, and this address signal is used to select the data register. You are supposed to select a register. and,
After this selection, the input data is provided along with the write signal,
The input data is gated by this write signal and is latched into the data register selected by the previously supplied address signal.

(Problems to be Solved by the Invention) In the conventional data input method described above, when a write signal is supplied, the data existing on the data bus is always latched into the data register as input data. Therefore, if the write signal malfunctions unintentionally, there is a problem that even non-true data existing on the data bus at the time of this malfunction will be latched.

More specifically, if noise appears on the write signal line when it is not supposed to be input, this noise will be identified as a write signal, and the write signal consisting of this noise will cause irregular data on the data bus. is erroneously latched and input to the data register. In addition, the data to be input is supplied together with a write signal under the control of a microcomputer, but even if the microcomputer goes out of control, the write signal may be accidentally sent from the microcomputer at an unexpected time when it is not supposed to be input. This erroneous write signal causes erroneous data on the data bus to be erroneously latched and input. If unauthorized data is input in this way, not only will the subsequent circuit that receives this data malfunction, but in some cases, there is a possibility that, for example, the drive transistor, etc. provided in the subsequent circuit may be destroyed. be. Conventionally, in order to prevent such a situation, various circuit countermeasures have been taken for the subsequent circuit, but such conventional circuit countermeasures are extremely complicated and uneconomical, and such circuit countermeasures are is not necessarily sufficient, and even if circuit countermeasures are taken, the circuit at the subsequent stage will stop operating whenever irregular input data as mentioned above is supplied, so the system is not sufficient. unable to perform any movements.

The present invention has been made in view of the above, and an object thereof is to provide a data input circuit that can accurately input only the data to be input without making any mistakes.

[Structure of the invention]

(Means for Solving the Problems) In order to solve the above problems, the present invention provides permission signal supply means for supplying a predetermined permission signal in advance of data to be input, and a set of permission signals following the permission signal. The gist of the present invention is to have a permission circuit for controlling so that only the input data of the above are effectively input.

(Operation) In the data input circuit of the present invention, only one set of input data after being supplied with a predetermined permission signal is effectively input.

(Example) Hereinafter, this invention will be described in detail using the drawings. 1st
The figure is a block diagram of a data input circuit according to an embodiment of the present invention. FIG. 2 is a waveform diagram of electrical signals of the data input circuit of FIG. 1.

In the data input circuit shown in FIG. 1, input data is supplied via a data bus 1 from, for example, a microcomputer.

A permission circuit 3, a selector 5, and a plurality of data registers 7 are commonly connected to this data bus 1. Also,
This data input circuit has a write circuit 9.

On the data bus 1, permission data, address signals and input data signals are sequentially supplied from, for example, a microcomputer as shown in FIG. The address signal is decoded by the selector 5, and this decoded signal specifies one of the plurality of data registers 7, and the input data signal is latched into the specified data register 7. .

As shown in FIG. 2, the write circuit 9 has a status signal synchronized to gate both the permission signal and the address signal, and three write signals synchronized with the permission data, address signal, and data signal, respectively. The write circuit 9 is configured to generate two command write signals synchronized with the permission data and address signals, respectively, and a data write signal synchronized with the data signal. The command write signal output from the write circuit 9 is supplied to the permission circuit 3 and the selector 5, and the data write signal is supplied to each data register 7 as a gate signal.

The permission circuit 3 gates and latches the permission data supplied from the data passco by a write signal and a command write signal, and transfers the permission signal from the rear end of the first command write signal to the next command write signal. This permission signal is output from the rear end of the gate and supplied to the selector 5.

The selector 5 latches the address signal on the data bus 1 according to the command write signal supplied when the enable signal from the enable circuit 3 is supplied, decodes this address signal, and generates a select signal 1.2°. 3 and are supplied to the corresponding data registers 7, respectively. Each of these select signals is output up to the rear end of the third write signal.

This data input circuit is configured as described above. Next, the effect will be explained.

First, before a data signal to be input is supplied, permission data and an address signal are sequentially supplied to the data passco, and a synchronized status signal is sent to the write circuit 9 so as to gate these permission data and address signals. supplied to

Further, the write circuit 9 is supplied with three write signals in synchronization with the permission data, address signal, and data signal supplied on the data bus 1 at the same time as this status signal. The write circuit 9 generates a first command write signal in synchronization with the permission data in response to the status signal and the first write signal, receives the permission data on the data pathco by this command write signal, and receives the permission data on the data pass code as shown in FIG. A permission signal as shown is supplied to the selector 5.

When the selector 5 receives a command write signal from the write circuit 9 while receiving this permission signal, it latches the address signal on the data bus 1 by this command write signal. Then, this address signal is decoded and the decoded select signal is output.

This select signal specifies one of the plurality of data registers 7, but as shown in FIG.
If a data write signal synchronized with the third write signal is supplied while this select signal is output to the rear end of the write signal, this data write signal causes the data specified by the select signal to be output. The data signal on the data bus 1 is latched into the designated data register 7, and is output from the designated data register 7.

In other words, in this data input circuit, the data bus 1 is connected only when permission data is supplied prior to the data signal.
The above data signal is regarded as a regular data signal, and is latched into the data register 7 and output.

FIG. 3 is a block diagram of a data input circuit according to another embodiment of the present invention, and FIG. 4 is a waveform diagram of electrical signals of the data input circuit of FIG. 3.

The basic configuration of this data input circuit is almost the same as the circuit shown in FIG. 1, but an enable signal is output in synchronization only with the permission data supplied to the data passco in the write circuit 9 of FIG. is newly supplied, a permission data write signal and an address write signal are independently output as output signals, and these signals are respectively supplied to the permission circuit 3 and the selector 5 instead of the command write signal in FIG. The only difference is that the write circuit 9' is configured as shown in FIG. 1, and the operation of this data input circuit is the same as that of the circuit shown in FIG.

As a result of this configuration, the write circuit 9 receives only the first write signal due to the enable signal, and thereby receives the fourth write signal.
As shown in the figure, a single permission data write signal is sent to the permission circuit 3.
It receives the permission data on the data bus 1 and outputs it as a permission signal. Therefore, as the command write signal is not shared between the permission circuit 3 and the selector 5 as shown in FIG. 1, the permission data supplied to the data bus 1 can be any arbitrary signal that is not limited by other signals such as address signals. can be used. Similarly, selector 5
The address write signal for latching the address signal is also formed independently as shown in Figure 4 due to the condition that there is no enable signal q and a status signal, so the address signal is limited to other signals. Any signal can be used.

In the data input circuit of this embodiment, even if, for example, a microcomputer that supplies input data goes out of control and an unintended enable signal is supplied, if the permission data do not match at this time, the permission signal will not be output. Therefore, this circuit will not operate. Furthermore, even if the permission data match, a status signal must be supplied next, and if a write signal is not supplied, the circuit will not operate normally, and unintended data will not be easily input. This is how it is.

FIG. 5 is a more detailed circuit of the data input circuit of FIG. 1, that is, a detailed circuit in which each block circuit of the data input circuit of FIG. 1 is developed in more detail using specific logic circuit elements, and the basic circuit is The operation is the same as that of the circuit of FIG.

FIG. 6 is a waveform diagram of electrical signals of the data input circuit of FIG. 5. Therefore, although FIG. 6 is a waveform diagram corresponding to the waveform diagram of FIG. 2, the polarity of the write signal is inverted and a new provisional permission signal is added.

In the data input circuit shown in FIG. 5, the write circuit 9 is composed of a D-type flip-flop 91 and an AND circuit 92. Note that the hidden circuit 9 shown in FIG. 1 is designed to generate a command write signal, but in FIG. 94, which is supplied to the clock input of the individual input type flip-flop 31 of the enable circuit 3, and is supplied to the clock input of the individual input type flip-flop 5 of the select circuit 5.
1 clock input. The individual input type flip-flop 31 of the permission circuit 3 latches the permission data on the data bus 1 according to the command write signal from the AND circuit 94, and supplies a temporary permission signal to the D-type flip-flop 33. The D-type flip-flop 33 latches this provisional permission signal as a read-in signal via the inverter 93, and supplies the permission signal to one input of each AND circuit 53 of the select circuit 5. The select circuit 5 has a D-type flip-flop 51 with one input for receiving an address signal supplied on the data bus 1, and latches the address signal in response to a command write signal from the AND circuit 94.

As a result, only one of the outputs of the multi-input flip-flop 51 becomes high level in response to the latched address signal, and this high level address signal is sent to the data register 7 as a select signal via the AND circuit 53. Only the corresponding AND circuit 71 is gated. on the other hand,
A data write signal from the AND circuit 92 of the write circuit 9 is supplied to this AND circuit 71, and the multi-input type flip-flop of the data register 7 is supplied with the data write signal from the AND circuit 92 of the write circuit 9. The input flip-flop 2 outputs the signal as an output signal.

FIG. 7 is a more detailed circuit of the data input circuit of FIG. 3, that is, a detailed circuit in which each block circuit of the data input circuit of FIG. 3 is developed in more detail using specific logic circuit elements, and the basic circuit is The operation is the same as that of the circuit shown in FIG.

FIG. 8 is a waveform diagram of electrical signals of the data input circuit of FIG. 7. Therefore, FIG. 8 is a waveform diagram corresponding to the waveform diagram of FIG. 4.

As explained in FIG. 3, the data input circuit of FIG. 7 is newly supplied with an enable signal that synchronizes only with the permission data on data bus 1, so that the permission data write signal and address write signal are separately input. It was formed. For this purpose, the circuit of FIG. 7 has a D-type flip 70 knob 95 that latches the enable signal, and supplies the output signals @Q and Q of this D-type flip 70 knob 95 to AND circuits 35 and 37, respectively, to enable the enable signal. A data write signal and an address write signal are formed separately and supplied to the clock inputs of the multi-input type flip-flop 70 tube 31 of the enable circuit 3 and the multi-input type flip-flop 51 of the select circuit 5, and the data bus 1 The above permission data and address signals are properly latched. Other circuit operations are the same as those in FIGS. 3 and 5.

〔Effect of the invention〕

As explained above, according to the present invention, only one set of input data after a predetermined permission signal is supplied is effectively input, so only the regular data that should be input after the permission signal is input. be done. Therefore, even if an erroneous write signal is supplied due to noise or runaway of the microcomputer as in the past, if the permission signal has not been supplied in advance,
This prevents unauthorized data from being input due to such an erroneous write signal, and particularly guarantees the safety of subsequent circuits.

[Brief Description of the Drawings] Fig. 1 is a block diagram of a data input circuit according to an embodiment of the present invention, Fig. 2 is a waveform diagram showing the operation of the circuit of Fig. 1,
FIG. 3 is a block diagram of a data input circuit according to another embodiment of the present invention, FIG. 4 is a waveform diagram showing the operation of the circuit in FIG. 3, and FIGS. 5 and 7 are similar to FIGS. 3 is a detailed circuit diagram, and FIGS. 6 and 8 are waveform diagrams showing the operation of the circuits of FIGS. 5 and 7, respectively. 1... Data bus 3... Enable circuit 5... Selector 7... Data register 9.9'...
Writing circuit fee 0 people 1 person Satoshi Miyoshi Tamotsu A Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] Data characterized by having a permission signal supply means for supplying a predetermined permission signal in advance of data to be input, and a permission circuit for controlling so that only one set of input data following the permission signal is effectively input. input circuit.