JPS6389254U - - Google Patents
Info
- Publication number
- JPS6389254U JPS6389254U JP18345186U JP18345186U JPS6389254U JP S6389254 U JPS6389254 U JP S6389254U JP 18345186 U JP18345186 U JP 18345186U JP 18345186 U JP18345186 U JP 18345186U JP S6389254 U JPS6389254 U JP S6389254U
- Authority
- JP
- Japan
- Prior art keywords
- package
- contact member
- transfer mold
- circuits
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 239000002184 metal Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18345186U JPS6389254U (US07579456-20090825-P00002.png) | 1986-11-28 | 1986-11-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18345186U JPS6389254U (US07579456-20090825-P00002.png) | 1986-11-28 | 1986-11-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6389254U true JPS6389254U (US07579456-20090825-P00002.png) | 1988-06-10 |
Family
ID=31130199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18345186U Pending JPS6389254U (US07579456-20090825-P00002.png) | 1986-11-28 | 1986-11-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6389254U (US07579456-20090825-P00002.png) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008227131A (ja) * | 2007-03-13 | 2008-09-25 | Renesas Technology Corp | 半導体装置及びその製造方法 |
| JP2013171848A (ja) * | 2012-02-17 | 2013-09-02 | Denso Corp | モールドパッケージおよびその製造方法 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56155555A (en) * | 1980-05-06 | 1981-12-01 | Seiko Epson Corp | Semiconductor device |
-
1986
- 1986-11-28 JP JP18345186U patent/JPS6389254U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56155555A (en) * | 1980-05-06 | 1981-12-01 | Seiko Epson Corp | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008227131A (ja) * | 2007-03-13 | 2008-09-25 | Renesas Technology Corp | 半導体装置及びその製造方法 |
| JP2013171848A (ja) * | 2012-02-17 | 2013-09-02 | Denso Corp | モールドパッケージおよびその製造方法 |
