JPS6388866A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a transistor having good controllability in a groove-digging type separating structure by forming a plurality of grooves for separating elements therebetween at an interval substantially in parallel on a semiconductor substrate, and forming a plurality of first impurity regions for controlling a threshold value voltage on the surface region between the first grooves on the substrate. CONSTITUTION:A plurality of grooves 21 for separating elements therebetween are formed at an interval substantially in parallel on a predetermined parts of a p<-> type semiconductor substrate 1. Then, a plurality of p<+> type impurity regions 31 for preventing an inversion and a parasitic are formed on the surface regions of the grooves 21. The grooves 21 are buried with separating insulating films 41 up to the surface of the substrate 1, and a gate electrode 71 is formed through a gate insulating film 61 on the regions between the grooves 21 on the films 41. Therefore, it is not necessary to form an impurity region for controlling a threshold value voltage on the surface region of the sidewalls of the grooves as the conventional one. Since an impurity region 51 can be easily formed in an uniform depth between the grooves 21 over the whole surface region of the substrate 1, a transistor having good controllability can be obtained in a groove-digging type separating structure.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to a semiconductor device in which transistors with good controllability are formed in a Mizohori isolation structure and a method for manufacturing the same. It is.

[Prior Art] FIG. 2A is a plan view showing a semiconductor device having a conventional m-moat type diagonal structure, FIG. 2B is a cross-sectional view taken along the line Y-Y' of FIG. 2A, and FIG. is a sectional view taken along the line Xl-X1' of Fig. 2.

In the figure, a plurality of device isolation devices 120 are formed at predetermined portions of a ρ-type semiconductor substrate 1 at intervals and substantially parallel to each other. A plurality of isolation insulating films 4o are provided at the bottom of the 8 grooves 20.
A plurality of p+ layers for inversion and parasitic prevention are formed in the bottom surface area of the eight grooves 20 surrounding each isolation insulating film 40.
A shaped impurity region 30 is formed. A plurality of n+ type impurity regions 80, 81 for the source and drain of an MO8 field effect transistor (hereinafter abbreviated as MO8FET) are formed in the surface region of the p-type semiconductor substrate 1 between the grooves 20, and each n+ type impurity region Territory! 80 and each n+ type impurity region 8
1 and are spaced apart from each other.

8 A predetermined portion of the surface area of the side wall portion of the groove 20, and each n+
A plurality of impurity regions 50 for controlling the threshold voltage of the MOSFET are formed in the surface region of the p - type semiconductor substrate 1 between the type impurity region 80 and each n + type impurity region 81 . A gate insulating film 60 is formed on the surface of each impurity region 50, the portion of the sidewall surface of the eight trenches 20 where no impurity region for threshold voltage control is formed, the surface of each n+ type impurity region 80, and the surface of each n+ type impurity region 81. It is formed. A gate electrode 70 is formed on the surface of the insulating film 60.

Each n+ type impurity region 80 and each n+ type impurity region 81 are located on both sides of the gate electrode 70, and each impurity region 5
0 is formed only under the gate electrode 70. here,
p- type semiconductor substrate 1, n+ type impurity region 80, n+ impurity region 81, gate insulating film 60, and gate t-'l pole 70.
! = constitutes MO8FET90.

[Problems to be Solved by the Invention] However, in conventional semiconductor devices, impurity ions must be implanted into the surface regions of about 20 sidewall portions to form impurity regions for threshold voltage control. With the normal ion implantation method, it is difficult to implant impurity ions to a uniform depth over the entire sidewall portion of the groove 20, which makes it difficult to form a MOSFET with good controllability. There was a point.

The present invention was made in order to solve the above-mentioned problems, and its object is to provide a semiconductor device having a transistor with good controllability in a trench isolation structure, and a method for manufacturing the same.

Measures to solve problem E] The semiconductor device according to the present invention has the following features.

That is, a semiconductor substrate of the 'jR1 conductivity type in which a plurality of first trenches for element isolation are formed in a predetermined part thereof at intervals and substantially parallel to each other, and a plurality of first trenches that fill each of the first trenches up to the surface of the semiconductor substrate. 1 isolation insulating film, and a plurality of second insulation films formed at the bottoms of the plurality of second isolation insulating films for element isolation formed continuously at both ends of each first trench in the direction of the first trench in the semiconductor substrate. an isolation insulating film, a plurality of first impurity regions for threshold voltage control formed in the surface region of the semiconductor substrate between the first trenches, and a source impurity region formed in the surface region of the semiconductor substrate between the second trenches. A plurality of second impurity regions of the second conductivity type for drains, a side wall surface of each second bulk, a surface of each first isolation insulating film, and each first impurity region.
A gate insulating film formed on the surface of the impurity region and the surface of each second impurity region, and a gate electrode formed on the surface of the gate insulating film on each negative isolation insulating film and on each first impurity region.

A method for manufacturing a semiconductor device according to the present invention includes forming a plurality of first trenches for isolation between elements in a predetermined portion of a semiconductor substrate of a first conductivity type, spaced apart from each other and substantially parallel to each other, and forming each first trench into a semiconductor substrate. A plurality of first isolation insulating films are filled up to the surface of the substrate, and a plurality of second trenches for element isolation are formed in the semiconductor substrate in the direction of the first trenches and continue at both ends of each first trench. A plurality of second isolation insulating films are formed at the bottom, a plurality of first impurity regions for threshold voltage control are formed in the surface region of the semiconductor substrate between the first trenches, and a plurality of first impurity regions are formed on the sidewall surface of each second trench, each A gate insulating film is formed on the surface of the first isolation insulating film, the surface of each first impurity region, and the surface of the semiconductor substrate between the second grooves, and a gate insulating film is formed on the surface of the gate insulating film on each of the first isolation insulating films and on each of the first impurity regions. An N pole is formed, and a source/source is formed in the surface area of the semiconductor substrate between the second grooves.
This is a method of forming a plurality of second conductivity type second impurity regions for drains.

[Function] In the invention of this semiconductor device, a plurality of first grooves for isolation between elements formed in a predetermined portion of a semiconductor substrate at intervals and substantially parallel to each other are connected to a plurality of first isolation insulating films up to the surface of the semiconductor substrate. Since the gate electrode is formed via the gate insulating film on each first isolation insulating film and on each region between the first trenches, the surface area of the side wall of the trench is filled with Also, there is no need to form an impurity region for threshold voltage control, and it is sufficient to form a plurality of first impurity regions for threshold voltage control in the surface region of the semiconductor substrate between the first grooves. Therefore, the depth of the first impurity region can easily be made uniform over the entire region.

In the invention of the method for manufacturing a semiconductor device, a plurality of first grooves for element isolation are formed in a semiconductor substrate at intervals and substantially parallel to each other, and a threshold voltage is applied to a surface area of the semiconductor substrate between the first grooves. Since a plurality of first impurity regions for control are formed, the depth of the first impurity regions can be easily made uniform over the entire region.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

1A to 1H are process plan views and cross-sectional views showing a method for manufacturing a semiconductor device having a trench-type isolation structure, which is an embodiment of the present invention, and FIG. 1B is a
Figure 1D is a cross-sectional view taken along the line X2-X2' of Figure 1C, Figure 11, Figure 1G and Figure 1H are cross-sectional views taken along the Y-Y' line of Figure 1E, and Xl- It is a sectional view taken along the line X1' and a sectional view taken along the line X2-X2'.

To explain this manufacturing method, first, a plurality of grooves 21 for element isolation are formed in a predetermined portion of the p-type semiconductor substrate 1 at intervals and substantially parallel to each other. Next, a plurality of p+ type impurity regions 31 for inversion/parasitic prevention are formed in the surface region of the eight grooves 21. Next, the eight grooves 21 are inserted into the p-type semiconductor substrate 1.
The surface is filled with a plurality of isolation insulating films 41 (FIGS. 1A and 1B). Next, a plurality of grooves 22 for element isolation are formed in the p-type semiconductor substrate 1 in the direction of the grooves 21, and are connected to both ends of the eight grooves 21.
form. Next, the bottom surface area of the 8-groove 22 is inverted and
A plurality of p+ type impurity regions 30 for preventing parasitic properties are formed.

Next, a plurality of isolation insulating films 40 are formed at the bottom of the multi-groove 22 so as to be surrounded by each p-type impurity region 30 (FIGS. 1C and 1D). Next, a plurality of impurity regions 51 for threshold voltage control are formed in the surface region of the p-type semiconductor substrate 1 for about 21 hours.
form. At this time, since the impurity region 51 is formed in the surface region of the p-type semiconductor substrate 1 by ion implantation, the depth of the impurity region 51 can be easily made uniform over the entire region.

Next, a gate insulating film 6 is formed on the side wall surface of the multi-groove 22, the surface of each isolation insulating film 41, the surface of each p+ type impurity region 31, the surface of each impurity region 51, and the surface of the p- type semiconductor substrate 1 in the groove 22.
form 1. Next, a gate electrode 71 is formed on the surface of the gate insulating film 61 on each isolation insulating film 41, on each p″ type impurity region 31, and on each impurity region 51. Next,
A plurality of n-type impurity regions 80, 81 for source and drain are formed in the surface region of the p-type semiconductor substrate 1 on both sides of the gate electrode 71 between the grooves 22. Here, the p-type semiconductor substrate 1, the n+decade impurity region 80, the n1-type impurity region 81, the gate insulating film 61, and the gate electrode 71 are MOSFETs.
ET (Figures 1E to 1H).

In this way, each! I21 is filled up to 1) - the surface of the semiconductor substrate 1 with each isolation insulating film 41, and a gate electrode 71 is formed on each isolation insulating film 41 and on each region between the trenches 21 via a gate insulating film 61. Therefore, there is no need to form an impurity region for threshold voltage control in the surface region of the side wall of the trench as in the conventional case, and an impurity region 51 is not required to be formed in the surface region of the p-type semiconductor substrate 1 between the trenches 21. can be easily formed with a uniform depth over the entire region, making it possible to create transistors with good controllability in the Mizohori isolation structure. I can.

In addition, in the above embodiment, the case where an n-channel transistor is formed as MO8F[E] is shown, but
The present invention can be applied to the case of forming a p-channel p-channel 1-transistor, and can also be applied to the case of forming other transistors other than MO8FET.

[Effects of the Invention] As described above, according to the invention of this semiconductor device, a plurality of first grooves for isolation between elements, which are formed in a predetermined portion of a semiconductor substrate at intervals and substantially parallel to each other, extend to the surface of the semiconductor substrate. Since a plurality of first isolation insulating films are filled and a gate electrode is formed on each first isolation insulating film and on each region between each first trench through a gate insulating film, the area between the first trenches is A plurality of first impurity regions for threshold voltage control may be formed in the surface region of the semiconductor substrate. Therefore, the depth of the first impurity region can easily be made uniform over the entire region, and a semiconductor device having a transistor with good controllability in a trench isolation structure can be obtained.

Further, according to the invention of the method for manufacturing a semiconductor device, a plurality of first grooves for isolation between elements are formed in the semiconductor substrate at intervals and substantially parallel to each other, and the surface area of the semiconductor substrate between the first grooves is formed. Since a plurality of first impurity regions for threshold voltage control are formed, the depth of the first impurity regions can be made uniform over the entire region. Therefore, it is possible to obtain a method of manufacturing a semiconductor device having a transistor with good controllability in a trench-type isolation structure.

[Brief explanation of the drawing]

1A to 1H are process plan views and cross-sectional views showing a method for manufacturing a semiconductor device having a trench-type isolation structure, which is an embodiment of the present invention, and FIG. 1B is a
Figure 1D is a cross-sectional view taken along the line X2-X2' of Figure 1C, and Figures 1F, 1G, and 1H are cross-sectional views taken along the Y-Y' line of Figure 1E, and Xl-X1. They are a cross-sectional view taken along the line ``X2-X2''. FIG. 2A is a plan view showing a semiconductor device having a conventional trench-type isolation structure, FIG. 2B is a cross-sectional view taken along the line Y-Y' in FIG. 2A, and FIG. It is a sectional view taken along the line X1'. In the figure, 1 is a p-type semiconductor substrate, 21 and 22 are grooves,
30.31 is a p+ dec type impurity region 40°41 is an isolation insulating film, 51 is an impurity region, 61 is a gate insulating film, 71 is a gate electrode, 80.81 is a 01 type impurity region, 91 is MO
It is an SFET. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (4)

[Claims] (1) A semiconductor substrate of a first conductivity type is provided, and a predetermined portion of the semiconductor substrate has a plurality of first semiconductor substrates for isolation between elements.
a plurality of first isolation insulating films that fill each of the first grooves up to the surface of the semiconductor substrate, the grooves being spaced apart from each other and substantially parallel; A plurality of second grooves for isolation between elements are formed at both ends of the first groove, and a plurality of second isolation insulating films formed at the bottom of each of the second grooves are formed between the plurality of second isolation insulating films formed at the bottom of each of the second grooves; a plurality of first impurity regions for threshold voltage control formed in the surface region of the semiconductor substrate; and a plurality of second impurity regions for source/drain formed in the surface region of the semiconductor substrate between the second grooves. a conductive type second impurity region; a sidewall surface of each of the second grooves; a surface of each of the first isolation insulating films;
a gate insulating film formed on the surface of each of the first impurity regions and the surface of each of the second impurity regions; and a gate insulating film formed on the surface of the gate insulating film on each of the first isolation insulating films and on each of the first impurity regions. A semiconductor device comprising a gate electrode. (2) Furthermore, an inverted groove is formed in the surface region of each of the first trenches and has an impurity concentration higher than that of the semiconductor substrate.
a plurality of third impurity regions of the first conductivity type for parasitic prevention; and a plurality of third impurity regions of the first conductivity type are formed in a surface region at the bottom of each of the second grooves so as to surround each of the second isolation insulating films, and the impurity region is lower than the impurity concentration of the semiconductor substrate. 2. The semiconductor device according to claim 1, further comprising a plurality of fourth impurity regions of the first conductivity type for inversion/parasitic prevention with high concentration. (3) forming a plurality of first grooves for isolation between elements in a predetermined portion of a semiconductor substrate of a first conductivity type, spaced apart from each other and substantially parallel to each other; filling with a first isolation insulating film; forming a plurality of second grooves for device isolation in the semiconductor substrate in the direction of the first grooves and extending from both ends of each of the first grooves; forming a plurality of second isolation insulating films at the bottom of the second trench; forming a plurality of first impurity regions for threshold voltage control in a surface region of the semiconductor substrate between the first trenches; a side wall surface of each of the second grooves, a surface of each of the first isolation insulating films,
forming a gate insulating film on the surface of the semiconductor substrate between the surface of each of the first impurity regions and the second trench; and forming a plurality of second impurity regions of a second conductivity type for sources and drains in a surface region of the semiconductor substrate between the second grooves. Method. (4) Further, forming a plurality of third impurity regions of the first conductivity type for inversion/parasitic prevention having an impurity concentration higher than the impurity concentration of the semiconductor substrate in the surface region of each of the first grooves; A plurality of fourth conductivity type fourth conductive films for inversion/parasitic prevention having an impurity concentration higher than the impurity concentration of the semiconductor substrate are arranged in the surface region at the bottom of each second trench so as to surround each of the second isolation insulating films.
4. The method of manufacturing a semiconductor device according to claim 3, further comprising the step of forming an impurity region.