JPS6388851A - Protective device for input - Google Patents
Protective device for inputInfo
- Publication number
- JPS6388851A JPS6388851A JP23493386A JP23493386A JPS6388851A JP S6388851 A JPS6388851 A JP S6388851A JP 23493386 A JP23493386 A JP 23493386A JP 23493386 A JP23493386 A JP 23493386A JP S6388851 A JPS6388851 A JP S6388851A
- Authority
- JP
- Japan
- Prior art keywords
- resistance layer
- polysilicon resistance
- polysilicon
- layer
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001681 protective effect Effects 0.000 title abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
- 229920005591 polysilicon Polymers 0.000 claims abstract description 32
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 29
- 230000000295 complement effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は入力保護装置に関し、特に−導電型不純物を含
むポリシリコン抵抗層を有する入力保護装置の形成法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input protection device, and more particularly to a method for forming an input protection device having a polysilicon resistance layer containing -conductivity type impurities.
従来例えば相補型ＭＯｓ構造における入力保護装置は例
えば第３図及び第４図に示すように、一端がポンディン
グパッド２１に接続されたＮ型不純物を含むポリシリコ
ン抵抗層１８と、Ｐ型ウェル１６中に塑成され一端がポ
リシリコン抵抗層１８とオーミック接続され、他端がゲ
ート入力へと通じるＮ型拡散層１７とから形成されてい
た。なお、Ｐ型ウェル１６はＶｓｓ電源線２４にオーミ
ック接続されている。また第４図のダイオードｌ）はＰ
型ウェル１６とＮ型拡散層１７とで形成されたものであ
る。Conventionally, for example, an input protection device in a complementary MOS structure has a polysilicon resistance layer 18 containing an N-type impurity, one end of which is connected to a bonding pad 21, and a P-type well 16, as shown in FIGS. It was formed of an N-type diffusion layer 17 which was molded into the inside and was ohmically connected to a polysilicon resistance layer 18 at one end, and connected to the gate input at the other end. Note that the P-type well 16 is ohmically connected to the Vss power supply line 24. Also, the diode l) in Fig. 4 is P
It is formed of a type well 16 and an N type diffusion layer 17.
上述した従来の入力保護装置は、一端をポンディングパ
ッドにオーミック接続し、他端をＮ型拡散抵抗層にオー
ミック接続したＮ型不純物を含むポリシリコン抵抗層が
絶縁層間膜中に単独で形成されているので、ポンディン
グパッドにサージ電圧が印加された場合に、ポリシリコ
ン抵抗層で発生するジュール熱の大部分はポリシリコン
抵抗層自体で消費され、ポリシリコン抵抗層が溶断しや
ずいという欠点がある。In the conventional input protection device described above, a polysilicon resistance layer containing an N-type impurity is formed singly in an insulating interlayer film, with one end ohmically connected to a bonding pad and the other end ohmically connected to an N-type diffused resistance layer. Therefore, when a surge voltage is applied to the bonding pad, most of the Joule heat generated in the polysilicon resistance layer is consumed by the polysilicon resistance layer itself, and the disadvantage is that the polysilicon resistance layer is difficult to melt. There is.
〔問題点を″ｐ＋イ決するだめの手段〕本発明の入力保
護装置は入力用ポンディングパッドに一端がオーミック
接続された一導電型不純物を含むポリシリコン抵抗層と
、前記ポリシリコン抵抗１−上部にコンタクト穴を介し
て前記ポリシリコン抵抗層とオーミック接続するように
形成された金属層を少くとも１ケ所以上有している。[Means to resolve the problem] The input protection device of the present invention includes a polysilicon resistance layer containing an impurity of one conductivity type and one end of which is ohmically connected to an input bonding pad, and At least one metal layer is formed to make an ohmic connection with the polysilicon resistance layer through a contact hole.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の相補型ＭＯ８集積回路における実施例
の平面図で第２図は第１図のＡ −Ａ’線上における１
新面図を示す。第１図及び第２図においてＰ型りエル１
内に形成されたＮ型拡散抵抗層２の一端とＮ型不純物を
含むポリシリコン抵抗層３の一端はコンタクト８により
オーミック接続されている。ポリシリコン抵抗層３の他
端は所定の抵抗値を得た後、ボンディングパット９とコ
ンタクト４を介してオーミック接続しており、一方Ｎ型
拡散抵抗層２の他端は所定の抵抗値を得た後入力ゲート
電極Ｇへと通じる。ポリシリコン抵抗層３の上部にはコ
ンタクト５．６．７を介してポリシリコン抵抗層３とオ
ーミック接続するようにアルミ層１０．１１．１２が形
成されている。FIG. 1 is a plan view of an embodiment of a complementary MO8 integrated circuit according to the present invention, and FIG.
A new view is shown. In Figures 1 and 2, P-type Riel 1
One end of the N-type diffused resistance layer 2 formed therein and one end of the polysilicon resistance layer 3 containing N-type impurities are ohmically connected through a contact 8 . After obtaining a predetermined resistance value, the other end of the polysilicon resistance layer 3 is ohmically connected to the bonding pad 9 via the contact 4, while the other end of the N-type diffused resistance layer 2 has a predetermined resistance value. After that, it leads to the input gate electrode G. Aluminum layers 10, 11 and 12 are formed on top of the polysilicon resistance layer 3 so as to be ohmically connected to the polysilicon resistance layer 3 via contacts 5, 6 and 7.
以上説明したように本発明は、ポリシリコン抵抗層上に
このポリシリコン抵抗層とオーミック接続するように金
属＃を形成することによシ、サージ電圧印加時にポリシ
リコン抵抗層で発生するジュール熱が、比較的熱伝導率
の高い金Ｍ層を介して周囲に放熱され、ポリシリコン抵
抗層の温度上昇を緩和してポリシリコン抵抗層が溶断す
るのを防ぎ入力保護能力を向上できる効果がある。As explained above, in the present invention, by forming metal # on the polysilicon resistance layer so as to make an ohmic connection with the polysilicon resistance layer, the Joule heat generated in the polysilicon resistance layer when a surge voltage is applied is reduced. The heat is radiated to the surroundings through the gold M layer, which has a relatively high thermal conductivity, and this has the effect of alleviating the temperature rise of the polysilicon resistance layer, preventing the polysilicon resistance layer from melting, and improving the input protection ability.
第１図は本発明による入力保護パターンの平面図であり
、第２図は第１図のＡ−Ａ″線における断面図である。
第３図は従来の入力保護パターンの平面図であり、第４
図は第３図の等価回路である。
１．１６・・・・・・Ｐ型ウェル、２．１７・・・・・
・Ｎ型拡散抵抗層、３，１８・・・・・・Ｎ型ポリシリ
コン抵抗層、４．５，６，７，８，１４，１９，２０．
２３・・・・・・コンタクトホール、９．２１・・・・
・・ボンディングパットアルミ、１０，１１．１２アル
ミ、１３．２２・・・・・・Ｐ型拡散層、１５ 、２４
・・・・・・Ｖｓｓ電源線。FIG. 1 is a plan view of an input protection pattern according to the present invention, and FIG. 2 is a cross-sectional view taken along line A-A'' in FIG. 1. FIG. 3 is a plan view of a conventional input protection pattern. Fourth
The figure is an equivalent circuit of FIG. 1.16...P-type well, 2.17...
・N-type diffused resistance layer, 3, 18...N-type polysilicon resistance layer, 4.5, 6, 7, 8, 14, 19, 20.
23...Contact hole, 9.21...
...Bonding pad aluminum, 10, 11.12 Aluminum, 13.22...P type diffusion layer, 15, 24
・・・・・・Vss power line.
Claims (1)
た一導電型の不純物を含むポリシリコン抵抗層を有する
入力保護装置において、前記ポリシリコン抵抗層上部に
コンタクト穴を介して前記ポリシリコン抵抗層とオーミ
ック接続するように形成された金属層を少くとも１ケ所
以上有することを特徴とする半導体集積回路の入力保護
装置。In an input protection device having a polysilicon resistance layer containing an impurity of one conductivity type, one end of which is ohmically connected to an input bonding pad, the polysilicon resistance layer is ohmically connected to the polysilicon resistance layer through a contact hole in the upper part of the polysilicon resistance layer. 1. An input protection device for a semiconductor integrated circuit, comprising at least one metal layer formed as described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23493386A JPS6388851A (en) | 1986-10-01 | 1986-10-01 | Protective device for input |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23493386A JPS6388851A (en) | 1986-10-01 | 1986-10-01 | Protective device for input |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6388851A true JPS6388851A (en) | 1988-04-19 |
Family
ID=16978547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23493386A Pending JPS6388851A (en) | 1986-10-01 | 1986-10-01 | Protective device for input |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6388851A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100485784B1 (en) * | 2002-10-24 | 2005-04-28 | 삼성전자주식회사 | A Magnetic Tape Extending Device of Tape Recorder |
-
1986
- 1986-10-01 JP JP23493386A patent/JPS6388851A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100485784B1 (en) * | 2002-10-24 | 2005-04-28 | 삼성전자주식회사 | A Magnetic Tape Extending Device of Tape Recorder |
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