JPS6386924A - Original exponent-vector converting circuit on galois body - Google Patents

Abstract

PURPOSE:to execute an exponent-vector conversion by a small circuit quantity, by constituting an exponent-vector converting circuit in a digital processing circuit, of a gate circuit and a multiplying circuit. CONSTITUTION:When a binary expression of a code length (n) has been sent in order of N0 N7, alphaN<0> alphaN<7>.<128> are outputted to a bus line Y, and sent to a multiplying circuit 2. From an output Z of the multiplying circuit 2, outputs multiplied by alphaN<0>-alphaN<7>.<128> are outputted successively. Its output is fetched in a register 3, and output to the other input terminal X of the multiplying circuit 2. Also, to X, the contents of the register are set in advance so that '1' is outputted, when Y has outputted alphaN<0> has been outputted first. When alphaN<7>.<128> has been outputted, alpha<n> is generated. A clock pulse HCK is outputted from a clock oscillator, while N0-N7 are being outputted. In this way, a conversion from an exponent expression (n) to a vector expression alpha<n> can be executed by a gate circuit and a multiplying circuit which have been simplified.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to digital processing circuits, and in particular to a Galois field (gaILois field), which is a set of elements that can perform four arithmetic operations such as addition, subtraction, multiplication, and division. (usually expressed as GF(q), where q is the number of elements).

[Prior art]

Conventionally, the exponent/vector conversion of the original on the Galois field is very complicated, so the exponent/vector conversion circuit generates an exponent/vector correspondence table in ROM (read-on memory) and performs the conversion process using that table. It was usual to do so.

[Problems with conventional technology]

However, ROM has a large circuit configuration and is therefore unsuitable for simplifying the circuit configuration. For this reason, there has been a desire for an index/vector conversion circuit that is simple to replace the ROM and has a small amount of circuitry.

Means for Solving Problem C) The present invention provides a simple exponent/vector conversion circuit that performs exponent/vector conversion of an element on a Galois field using a gate circuit and a multiplication circuit without using a ROM. With the goal.

〔Example〕

Examples of the present invention will be described below.

In the exponent/vector conversion circuit, the exponent n is input in binary and is expressed as follows.

It is then decomposed as follows to generate αn.

n=N7・12B+N8・64+N5・32+N4・1
6+N3・8+N2・4+N1・2+NO・1 α0=αN? , 12a・αN6°64・αN5-3
2 ・αN4・16- a N 3°a, a N
2°4・αN1−2・αN.

Therefore, when Ni (i=o...7) is 1, α2"1
It is sufficient to construct a circuit that outputs 1 when the value is 0, and then sequentially bundles the outputs. Its block diagram is shown in FIG. 1, and its operation timing is shown in FIG. When a binary representation of code length n is sent in the order NO→N7, the path line Y has αNO−αN? The bow 28 is output and sent to the multiplication circuit 2. From the output Z of the multiplier circuit 2, αN0
~αN? The output multiplied by the bow 211 is output. The output is taken into the register 3 and outputted to the other input terminal X of the multiplication circuit 2. However, the contents of the register are set in X so that 1 is output when Y first outputs αN0. When αN7°126 is output, α0 is generated.

HCK is a clock pulse that is output from a clock oscillator (not shown) while NO to N7 are being output.

FIG. 3 shows the configuration of the index/vector circuit 1 which outputs the αN0 to N7 bows 26 according to NO to N.

Conventionally, this circuit was generated by a ROM, but in this embodiment, it is constructed by a gate circuit. In FIG. 3, the opening indicates an exclusive OR (exclusive OR) circuit, and the symbol + indicates a pass line. In the circuit of Figure 3, the irreducible polynomial is p (x)"x' +x4 +x3 +x"
+1, N i = 1 (i = O → 7
) (When D, sequentially a=(010oooooo), α”
= (00100000).

a' = (00001000), aa-(10111
000), a′6=(00110010), a”=(1
0111001), a64=(11111010), a
The gate circuit has a configuration that outputs ``' = (totoooot) and outputs 1 when N1=0.

With the above configuration, from the exponential representation n, the vector representation α
Conversion to 0 can be performed by simplified gate circuits and multiplier circuits.

Figure 1 (D) In the example, 8 clock inputs are required to serially output NoNN7 by the time α0 is generated, but if you want to reduce the number of clock inputs, output NO~N7 in parallel and adjust the multiplication circuit accordingly. The clock can also be manually operated by using a plurality of clocks.In that case, the amount of circuitry will be somewhat larger than in this embodiment.

〔Effect of the invention〕

As explained above, since the exponent/vector conversion circuit of the present invention is constituted by a gate circuit and a multiplication circuit, it has the advantage of being able to perform exponent/vector conversion with a small amount of circuitry.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an index/vector conversion circuit according to an embodiment of the present invention, FIG. 2 is an operation timing chart of the block diagram of FIG. 1, and FIG. 3 is a diagram showing the configuration of the index/vector circuit. . 1 ----1 index/vector circuit 2 ----1 multiplication circuit 3 -------Register

Claims (1)

[Claims] Binary representation of original index on Galois field GF(2^m) n=2^m^-^1・N_m_-_1+2^m^-^2
・Corresponding to Ni (i=0...m-1)=1 of N_m_-_2+...+2・N_1+N_0 ▲ Formula,
It consists of a circuit means that outputs ▼ and outputs 1 in response to Ni=0, and a multiplier circuit that sequentially multiplies the output of the circuit means, and a vector representation of n ▲ Mathematical formula, chemical formula , tables, etc. ▼ An original exponent/vector conversion circuit on a Galois field, which is characterized by generating and outputting .